74ALVC14 Datasheet, PDF (1/16 Pages) NXP Semiconductors – Hex inverting Schmitt trigger

74ALVC14
Hex inverting Schmitt trigger
Rev. 03 — 15 February 2005
Product data sheet
1. General description
The 74ALVC14 is a high-performance, low-power, low-voltage, Si-gate CMOS device and
superior to most advanced CMOS compatible TTL families.
The 74ALVC14 provides six inverting buffers with Schmitt-trigger action. It is capable of
transforming slowly changing input signals into sharply defined, jitter-free output signals.
2. Features
s Wide supply voltage range from 1.65 V to 3.6 V
s 3.6 V tolerant inputs/outputs
s CMOS low power consumption
s Direct interface with TTL levels (2.7 V to 3.6 V)
s Power-down mode
s Unlimited input rise and fall times
s Latch-up performance exceeds 250 mA
s Complies with JEDEC standard:
x JESD8-7 (1.65 V to 1.95 V)
x JESD8-5 (2.3 V to 2.7 V)
x JESD8-B/JESD36 (2.7 V to 3.6 V)
s ESD protection:
x HBM EIA/JESD22-A114-B exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V
s Multiple package options
3. Quick reference data
Table 1:
Symbol
t_PHL, t_PLH
Quick reference data
Parameter
propagation delay nA
to nY
Conditions
V_CC = 1.8 V; C_L = 30 pF;
R_L = 1 kΩ
V_CC = 2.5 V; C_L = 30 pF;
R_L = 500 Ω
V_CC = 2.7 V; C_L = 50 pF;
R_L = 500 Ω
V_CC = 3.3 V; C_L = 50 pF;
R_L = 500 Ω
Min Typ Max Unit
-
2.9 -
ns
-
2.2 -
ns
-
2.8 -
ns
-
2.4 -
ns