74AHC594 Datasheet, PDF (1/29 Pages) NXP Semiconductors – 8-bit shift register with output register

74AHC594; 74AHCT594
8-bit shift register with output register
Rev. 01 — 4 July 2006
Product data sheet
1. General description
The 74AHC594; 74AHCT594 is a high-speed Si-gate CMOS device and is pin compatible
with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7A.
The 74AHC594; 74AHCT594 is an 8-bit, non-inverting, serial-in, parallel-out shift register
that feeds an 8-bit D-type storage register. Separate clocks (SHCP and STCP) and direct
overriding clears (SHR and STR) are provided on both the shift and storage registers.
A serial output (Q7S) is provided for cascading purposes.
Both the shift and storage register clocks are positive-edge triggered. If the user wishes to
connect both clocks together, the shift register will always be one count pulse ahead of the
storage register.
2. Features
s Wide supply voltage range from 2.0 V to 5.5 V
s 8-bit serial-in, parallel-out shift register with storage
s Independent direct overriding clears on shift and storage registers
s Independent clocks for shift and storage registers
s Latch-up performance exceeds 100 mA per JESD 78 Class II
s Input levels:
x CMOS levels: 74AHC594 only
x TTL levels: 74AHCT594 only
s ESD protection:
x HBM JESD22-A114-C exceeds 2000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101-C exceeds 1000 V
s Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Applications
s Serial-to parallel data conversion
s Remote control holding register