74AHC2G32 Datasheet, PDF (1/16 Pages) NXP Semiconductors – Dual 2-input OR gate

74AHC2G32; 74AHCT2G32
Dual 2-input OR gate
Rev. 01 — 23 February 2004
Product data sheet
1. General description
The 74AHC2G/AHCT2G32 is a high-speed Si-gate CMOS device. This device provides
two 2-input OR gates.
2. Features
s Symmetrical output impedance
s High noise immunity
s ESD protection:
x HBM EIA/JESD22-A114-A exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V
x CDM EIA/JESD22-C101 exceeds 1000 V.
s Low power dissipation
s Balanced propagation delays
s SOT505-2 and SOT765-1 package
s Specified from −40 °C to +85 °C and −40 °C to +125 °C.
3. Quick reference data
Table 1: Quick reference data
GND = 0 V; T_amb = 25 °C; t_r = t_f ≤ 3.0 ns.
Symbol Parameter
Conditions
Type 74AHC2G
t_PHL, t_PLH
propagation delay
nA and nB to nY
C_I
input capacitance
C_PD
power dissipation
capacitance
Type 74AHCT2G
C_L = 15 pF;
V_CC = 5 V
C_L = 50 pF;
f_i = 1 MHz
t_PHL, t_PLH
C_I
C_PD
propagation delay
nA and nB to nY
input capacitance
power dissipation
capacitance
C_L = 15 pF;
V_CC = 5 V
C_L = 50 pF;
f_i = 1 MHz
Min Typ Max Unit
-
-
[1] [2] _-
3.2
5.5
ns
1.5
10
pF
16
-
pF
-
-
[1] [2] _-
3.3
6.9
ns
1.5
10
pF
17
-
pF
[1] C_PD is used to determine the dynamic power dissipation (P_D in µW).
P_D = C_PD × V_CC2 × f_i × N + Σ(C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz;
f_o = output frequency in MHz;