PI3PCIE3412 Datasheet, PDF (9/10 Pages) Pericom Semiconductor Corporation – 3.3V, PCI Express 3.0 2-Lane, 2:1 Mux/DeMux Switch, with Single Enable

PI3PCIE3412
PCI Express® 3.0 2-Lane,
2:1 Mux/DeMux Switch with Single Enable
DP1.2 Application
5
4
3
3V3_1
D
DP Source 1
DP
TX
C
Vbias_TX
50
(0 - 1.2V)
50
DP_LANEx
DP_LANEx#
Same goes for
other 3 lanes
DP_AUX
Vbias_TX
50
AUX
(0 - 1.2V)
TX
B
50
DP_AUX#
AUX
RX
DP_HPD
A
SEL_GPIO1
5
4
3V3_1
U101
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
GND
A0+
A0-
GND
VDD
A1+
A1-
VDD
SEL
GND
A2+
A2-
VDD
GND
A3+
A3-
GND
B0+
B0-
B1+
B1-
C0+
C0-
C1+
C1-
VDD
B2+
B2-
B3+
B3-
C2+
C2-
C3+
C3-
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
PI3PCIE3412
VDD and GND pins should be
shorted to PCB power planes
via shortest paths.
5V_1 and 3V3_1 should be
employed at the same time.
AUX_P1
AUX_P2
DP_AUX
AUX_N1
AUX_N2
DP_AUX#
U102
1
2
3
4
5
6
7
8
IN VDD
S1A #EN
S2A S1D
DA S2D
S1B DD
S2B S1C
DB S2C
GND DC
5V_1
16
15
14
13
12
11
10
9
PI5V330
C131 0.1u_0402
HPD1
HPD2
DP_HPD
3
2
1
At least 1pc 4.7uF and 4pc 0.1uF
decoupling capacitors are
recommended.
Each decoupling capacitor should
be connected to PCB power plane
via shortest path.
D
3V3_1
J101
3V3_1
C111
C112
C113
C114
C115
C116
C117
C118
AUX_N1
AUX_P1
0.1u_0402
0.1u_0402
0.1u_0402
0.1u_0402
0.1u_0402
0.1u_0402
0.1u_0402
0.1u_0402
C107
C108
C109
C110
0.1u_0402
1u_0805
0.1u_0402
0.1u_0402
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LCD_VCC
LCD_VCC
LCD_VCC
H_GND
AUX_CH_N
AUX_CH_P
H_GND
Lane0_P
Lane0_N
H_GND
Lane1_P
Lane1_N
H_GND
Lane2_P
Lane2_N
H_GND
Lane3_P
Lane3_N
H_GND
NC
LCD_VCC
LCD_Self_Test
LCD_GND
LCD_GND
LCD_GND
LCD_GND
HPD
BL_GND
BL_GND
BL_GND
BL_GND
BL_ENABLE
BL_PWM_DIM
NC
NC
BL_PWR
BL_PWR
BL_PWR
BL_PWR
NC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
4Lane eDP Source Receptacle
HPD1
C
3V3_1
J102
3V3_1
C123
C124
C125
C126
C127
C128
C129
C130
AUX_N2
AUX_P2
0.1u_0402
0.1u_0402
0.1u_0402
0.1u_0402
0.1u_0402
0.1u_0402
0.1u_0402
0.1u_0402
C119
C120
C121
C122
0.1u_0402
1u_0805
0.1u_0402
0.1u_0402
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LCD_VCC
LCD_VCC
LCD_VCC
H_GND
AUX_CH_N
AUX_CH_P
H_GND
Lane0_P
Lane0_N
H_GND
Lane1_P
Lane1_N
H_GND
Lane2_P
Lane2_N
H_GND
Lane3_P
Lane3_N
H_GND
NC
LCD_VCC
LCD_Self_Test
LCD_GND
LCD_GND
LCD_GND
LCD_GND
HPD
BL_GND
BL_GND
BL_GND
BL_GND
BL_ENABLE
BL_PWM_DIM
NC
NC
BL_PWR
BL_PWR
BL_PWR
BL_PWR
NC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
4Lane eDP Source Receptacle
HPD2
B
A
Title
PI3PCIE3412 4Lane eDP 1:2 Application Circuit wi0t-h1.2Vbias
Size Document Number
Rev
A
Date:
Tuesday, March 06, 2012 Sheet
1 of 4
2
1
13-0046
9
www.pericom.com 04/15/13