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PI7C8150B_15 Datasheet, PDF (77/107 Pages) Pericom Semiconductor Corporation – ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
14.1.5
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
REVISION ID REGISTER – OFFSET 08h
Bit
Function
7:0
Revision
Type
R/O
Description
Indicates revision number of device. Hardwired to 02h
14.1.6
CLASS CODE REGISTER – OFFSET 08h
Bit
15:8
23:16
31:24
Function
Programming
Interface
Sub-Class Code
Base Class Code
Type
R/O
R/O
R/O
Description
Read as 0 to indicate no programming interfaces have been defined
for PCI-to-PCI bridges
Read as 04h to indicate device is PCI-to-PCI bridge
Read as 06h to indicate device is a bridge device
14.1.7
14.1.8
CACHE LINE SIZE REGISTER – OFFSET 0Ch
Bit
Function
Type Description
7:0
Cache Line Size R/W
Designates the cache line size for the system and is used when
terminating memory write and invalidate transactions and when
prefetching memory read transactions.
Only cache line sizes (in units of 4-byte) which are a power of two
are valid (only one bit can be set in this register; only 00h, 01h, 02h,
04h, 08h, and 10h are valid values).
Reset to 0
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch
Bit
Function
Type Description
15:8 Primary Latency R/W This register sets the value for the Master Latency Timer, which
timer
starts counting when the master asserts FRAME_L.
Reset to 0
14.1.9
HEADER TYPE REGISTER – OFFSET 0Ch
Bit
Function
23:16 Header Type
Type
R/O
Description
Read as 01h to indicate that the register layout conforms to the
standard PCI-to-PCI bridge layout.
14.1.10
PRIMARY BUS NUMBER REGISTSER – OFFSET 18h
Bit
Function
7:0
Primary Bus
Number
Type
R/W
Description
Indicates the number of the PCI bus to which the primary interface
is connected. The value is set in software during configuration.
Reset to 0
14.1.11
SECONDARY BUS NUMBER REGISTER – OFFSET 18h
Bit
Function
15:8 Secondary Bus
Number
Type
R/W
Description
Indicates the number of the PCI bus to which the secondary
interface is connected. The value is set in software during
configuration.
Reset to 0
15-0048
Page 77 of 107
April 2015 – Revision 2.1