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PT7M8202 Datasheet, PDF (7/11 Pages) Pericom Semiconductor Corporation – LDO Regulator
PT7M8202
LDO Regulator
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Function block diagram
EN
VIN
OvOevre-rc-ucurrrreenntt/Over
Temperature
PPrrotoetceticotinoCnirCciurict uit
OON//OOFFFF
CCirirccuui tit
QQuuiicckkSSttaarrt t
RReeffeerreenncece
VVoollttaaggeeCCi ricruciut it
VOUT
GND
BP
Functional Description (Refer to Function Block Diagram)
Output Voltage
The divided output voltage is compared with the internal reference voltage by the error amplifier with internal phase compensator.
The output of the error amplifier then drives the P-channel MOSFET to maintain a stable and constant output voltage.
Low ESR Capacitors
The internal phase compensator maintains the stable output voltage with low ESR ceramic input and output capacitors. 1F low
ESR (X5R/X7R) ceramic capacitor located as close as possible to the IC’s pins is recommended.
Current Limit and Thermal Shutdown Protections
Current limit protection is used to limit the output current when an overload condition occurs. As a result, the output voltage will
drop. Thermal shutdown protection will turn off the output to reduce the power dissipation when the operation junction
temperature exceeds 170°C.
Bypass Capacitor and Low Noise
A 22nF between the BP pin and GND pin significantly reduces noise on the regulator output, it is critical that the capacitor
connection between the BP pin and GND pin be direct and PCB traces should be as short as possible. There is a relation ship
between the bypass capacitor value and the LDO regulator turn on time. DC leakage on this pin can affect the LDO regulator
output noise and voltage regulation performance.
EN Pin
The output of the regulator in PT7M8202A/B can be controlled with EN pin. The EN pin should be connected to a “VIN” or a
“GND” voltage as a floating input applied to inverter input of the enable circuitry will increase the current consumption.
 NOTE ON USE
1. Please use this IC within the stated absolute maximum ratings.
2. Where wiring impedance is high, operations may become unstable due to noise and/or phase lag depending on output current.
Please keep the resistance low between VIN and GND wiring in particular.
3. Please wire the input capacitor (Cin) and the output capacitor (Cout) as close to the IC as possible.
12-07-0004
PT0338-1
07/10/12
7