PT7C4302_15 Datasheet, PDF (7/14 Pages) Pericom Semiconductor Corporation – Real-time Clock Module (3-wire Interface)

PT7C4302
Real-time Clock Module (3-wire Interface)
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Registers
1. Allocation of registers
Addr.
(hex)
*1
Function
00 Seconds (00-59)
Bit 7
/EOSC^*2
Bit 6
S40
01 Minutes (00-59)
0
M40
02 Hours (00-23 / 01-12)
12, /24
0
03 Dates (01-31)
0
0
04 Months (01-12)
0
0
05 Days of the week (01-07)
0
0
06 Years (00-99)
07 Control
08 Trickle charger
1F Clock burst^*7
20~3E RAM^*9
3F
RAM burst^*8
Y80
WP^*3
TCS^*4
Y40
0
TCS
-
-
-
-
-
-
Register definition
Bit 5
Bit 4
Bit 3
S20
S10
S8
M20
M10
M8
H20 or
H10
H8
P /A
D20
D10
D8
0
MO10 MO8
0
0
0
Y20
Y10
Y8
0
0
0
TCS
TCS
DS^*5
-
-
-
-
-
-
-
-
-
Bit 2
S4
M4
H4
D4
MO4
W4
Y4
0
DS
-
-
-
Bit 1
S2
M2
H2
D2
MO2
W2
Y2
0
RS^*6
-
-
-
Bit 0
S1
M1
H1
D1
MO1
W1
Y1
0
RS
-
-
-
Caution points:
*1. PT7C4302 uses 5 bits for address. It’s address byte consists of 1 + RAM/Clock select bit +5-bit addr. + Read/Write select bit.
*2. Oscillator Enable bit. When this bit is set to 1, oscillator is stopped but time count chain is still active.
*3. WP: Write Protect bit. WP bit should be cleared before attempting to write to the device.
*4. TCS: Trickle Charger Select.
*5. DS: Diode Select.
*6. RS: Resistor Select.
*7. Clock burst register address is used as clock/calendar burst mode operation address for consecutively read/write 0~7H
registers. Clock/calendar burst mode operation can continuously read 0H to maximum 7H registers in order; write 0~7H registers
in order. Less or larger than 8 bytes in clock burst write mode are ignored.
*8. RAM burst register address is used as RAM burst mode operation address for consecutively read/write 20~3EH RAM. Less
than 31 bytes in RAM burst read/write mode are valid.
*9. PT7C4302 has 318 static RAM for customer use. It is volatile RAM.
*10. All bits marked with "0" are read-only bits. Their value when read is always "0". All bits marked with "-" are customer
using space.
2015-11-0004
PT0225-6 11/25/15
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