PT7C4302 Datasheet, PDF (5/16 Pages) Pericom Semiconductor Corporation – Real-time Clock Module (3-wire Interface)

Data Sheet
PT7C4302
Real-time Clock Module (3-wire Interface)
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Registers
1. Allocation of registers
Addr.
(hex) ^*1
Function
00 Seconds (00-59)
Register definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/EOSC^*2 S40
S20
S10
S8
S4
S2
S1
01 Minutes (00-59)
0
M40
M20
M10
M8
M4
M2
M1
H20 or
02 Hours (00-23 / 01-12)
12, /24
0
H10
H8
H4
H2
H1
P /A
03 Dates (01-31)
0
0
D20
D10
D8
D4
D2
D1
04 Months (01-12)
0
0
0
MO10 MO8 MO4 MO2 MO1
05 Days of the week (01-07) 0
0
0
0
0
W4
W2
W1
06 Years (00-99)
Y80
Y40
Y20
Y10
Y8
Y4
Y2
Y1
07 Control
WP^*3
0
0
0
0
0
0
0
08 Trickle charger
TCS^*4
TCS
TCS
TCS
DS^*5
DS
RS^*6
RS
1F Clock burst^*7
-
-
-
-
-
-
-
-
20~3E RAM^*9
-
-
-
-
-
-
-
-
3F RAM burst^*8
-
-
-
-
-
-
-
-
Caution points:
*1. PT7C4302 uses 5 bits for address. It’s address byte consists of 1 + RAM/Clock select bit +5-bit addr. + Read/Write select bit.
*2. Oscillator Enable bit. When this bit is set to 1, oscillator is stopped but time count chain is still active.
*3. WP: Write Protect bit. WP bit should be cleared before attempting to write to the device.
*4. TCS: Trickle Charger Select.
*5. DS: Diode Select.
*6. RS: Resistor Select.
*7. Clock burst register address is used as clock/calendar burst mode operation address for consecutively read/write 0~7H
registers. Clock/calendar burst mode operation can continuously read 0H to maximum 7H registers in order; write 0~7H registers
in order. Less or larger than 8 bytes in clock burst write mode are ignored.
*8. RAM burst register address is used as RAM burst mode operation address for consecutively read/write 20~3EH RAM. Less
than 31 bytes in RAM burst read/write mode are valid.
*9. PT7C4302 has 31×8 static RAM for customer use. It is volatile RAM.
*10. All bits marked with "0" are read-only bits. Their value when read is always "0". All bits marked with "-" are customer
using space.
PT0225(11/05)
5
Ver: 0