PI6C10806B Datasheet, PDF (5/13 Pages) Pericom Semiconductor Corporation – 1.8V/2.5V/3.3V, 100MHz, Low Skew 1:6 Crystal to LVCMOS Clock Buffer

PI6C10806B
1.8V/2.5V/3.3V, 100MHz, Low Skew 1:6 Crystal to LVCMOS Clock Buffer
2.5V Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines only, not tested.)
Note:
Storage Temperature........................................................... –65°C to +150°C _{Stresses greater than those listed under MAXIMUM}
V_DD, V_DDO Voltage................................................................–0.5V to +3.6V
Output Voltage (max. 3.6V)........................................... –0.5V to V_DD+0.5V
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
Input Voltage (max 3.6V).............................................. –0.5V to V_DD+0.5V
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
2.5V I/O DC Characteristics (Over Operating Range: V_DD = 2.5V ± 5%, T_A = -40° to 85°C)
Parameters
Description
Test Conditions⁽¹⁾
Min.
V_DDO I/O Supply Voltage
2.375
V_IH
Input HIGH Voltage Logic HIGH level
1.7
V_IL
Input LOW Voltage Logic LOW level
-0.3
V_OH
Output High Voltage
V_DDO = Min., V_IN = V_IH or V_IL
I_OH = -1mA
I_OH = -8mA
2
2
V_OL
Output LOW Voltage V_DDO = Min., V_IN = V_IH or V_IL
Notes:
1. For Max. or Min. conditions, use appropriate operating range values.
2. Typical values are at V_DD =3.3V, +25°C ambient and maximum loading.
I_OL = 1mA
I_OL = 8mA
Typ. ⁽²⁾
2.5
Max. Units
2.625
V_DD+0.3 _V
0.7
V
0.4
0.4
2.5V I/O AC Characteristics (Over Operating Range: V_DD/V_DDO = 2.5V ± 5%, T_A = -40° to 85°C)
Parameters
Description
Test Conditions⁽¹⁾ Min.
Typ
f_OUT
Output Frequency
Using Crystal
10
External Clock⁽²⁾
0
t_DC
Output Duty Cycle
@ V_DDO/2
47
t_R/t_F
RMS
CLKn Rise/Fall Time
Random RMS Phase Jitter
20% to 80%
150
25MHz @ Integration
Range
0.112
100Hz - 1MHz
t_SK(O)(3)
t_DIS,t_EN^{( 4)}
Output to Output Skew between any two
outputs of the same device @ same transition
Output Enable/Disable
@V_DDO/2
@V_DDO/2
Max.
50
100
55
800
Units
MHz
%
ps
ps
80
ps
4 cycles
Notes:
1. Unless noted otherwise, all parameters are tested with xtal @ f <= Fxtal_max,; outputs are terminated @ 50Ω to V_DDO/2, see waveforms.
2. External clock source is driving XTAL_IN input
3. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade.
4. These parameters are guaranteed, but not tested. Max delay is 4 cycles. Min. setup time = 3ns.
10-0151
5
PS9038C
06/29/10