PT7M1233 Datasheet, PDF (4/7 Pages) Pericom Semiconductor Corporation – Supervisory Circuit

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Block Diagram
Vcc
VCC Resistor
Divider
T.C.
Reference
PT7M1233/1233A
Supervisory Circuit
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Reset
Monitor
Timing
Delay
5k
RST
GND
Function Description
Power Monitor
A microprocessor’s (µP’s) reset input starts the µP in a known state. Whenever the µP is in an unknown state, it should be held in
reset. The supervisory circuits assert reset during power-up and prevent code execution errors during power-down or brownout
conditions.
On power-up, once Vcc reaches about 1.0V, RST is a guaranteed logic low of 0.4V or less. As Vcc rises, RST stays low. When
Vcc rises above the reset threshold V_RST, an internal timer releases RST after about 200ms. RST asserts whenever Vcc drops
below the reset threshold, i.e. brownout condition. If brownout occurs in the middle of a previously initiated reset pulse, the pulse
continues for at least another 200ms. On power-down, once Vcc falls below the reset threshold, RST stays low and is guaranteed
to be 0.4V or less until Vcc drops below 1V.
Reset Output: Bi-direction
PT7M1233
The devices provide RST output pin for a pushbutton switch. When the devices are not in a reset cycle, it continuously monitors
the RST signal for a low going edge. If an edge is detected, the devices will debounce the switch by pulling the RST line low.
After the internal timer has expired, the devices will continue to monitor the RST line. If the line is still low, they will continue to
monitor the line looking for a rising edge. Upon detecting a release, they will force the RST line low and hold it low for 200ms.
PT7M1233A
When an out-of-tolerance condition is detected, an internal power fail signal is generated which forces reset to the active state.
When V_CC returns to an in-tolerance condition, the reset signal is kept in the active state for approximately 200ms to allow the
power supply and processor to stabilize. The second function of the PT7M1233A is pushbutton reset control. The PT7M1233A
debounces a pushbutton closure and will generate a 200ms reset pulse upon release.
2013-06-0001
PT0195-4 06/17/13
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