PI7C7300 Datasheet, PDF (33/109 Pages) Pericom Semiconductor Corporation – 3-PORT PCI-to-PCI BRIDGE

4.8.4
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
When PI7C7300A detects a Type 1 configuration transaction intended for a PCI bus
downstream from the secondary bus, PI7C7300A forwards the transaction unchanged to
the secondary bus. Ultimately, this transaction is translated to a Type 0 configuration
command or to a special cycle transaction by a downstream PCI-to-PCI bridge.
Downstream Type 1 to Type 1 forwarding occurs when the following conditions are met
during the address phase:
! The lowest two address bits are equal to 01b.
! The bus number falls in the range defined by the lower limit (exclusive) in the
secondary bus number register and the upper limit (inclusive) in the subordinate bus
number register.
! The bus command is a configuration read or write transaction.
PI7C7300A also supports Type 1 to Type 1 forwarding of configuration write
transactions upstream to support upstream special cycle generation. A Type 1
configuration command is forwarded upstream when the following conditions are met:
! The lowest two address bits are equal to 01b.
! The bus number falls outside the range defined by the lower limit (inclusive)
in the secondary bus number register and the upper limit (inclusive) in the
subordinate bus number register.
! The device number in address bits AD[15:11] is equal to 11111b.
! The function number in address bits AD[10:8] is equal to 111b.
! The bus command is a configuration write transaction.
The PI7C7300A forwards Type 1 to Type 1 configuration write transactions as delayed
transactions. Type 1 to Type 1 configuration write transactions are limited to a single
data transfer.
SPECIAL CYCLES
The Type 1 configuration mechanism is used to generate special cycle transactions in
hierarchical PCI systems. Special cycle transactions are ignored by acting as a target and
are not forwarded across the bridge. Special cycle transactions can be generated from
Type 1 configuration write transactions in either the upstream or the down-stream
direction.
PI7C7300A initiates a special cycle on the target bus when a Type 1 configuration write
transaction is being detected on the initiating bus and the following conditions are met
during the address phase:
! The lowest two address bits on AD[1:0] are equal to 01b.
! The device number in address bits AD[15:11] is equal to 11111b.
! The function number in address bits AD[10:8] is equal to 111b.
Page 33 OF 109
09/25/03 Revision 1.09