PI7C7100 Datasheet, PDF (33/132 Pages) Pericom Semiconductor Corporation – 3-Port PCI Bridge

ADVANCE INFORMATION
PI7C7100
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Table 4-8. Responses to Posted Write Target Termination
Target Termination
Response
Normal
No additional action.
Target retry
Repeating write transaction to target.
Target disconnect
Initiate write transaction for delivering remaining posted write data.
Target abort
Set received-target-abort bit in the target interface status register. Assert
P_SERR# if enabled, and set the signaled-system-error bit in primary status
register.
Note that when a target retry or target disconnect is returned and posted write data associated with that transaction
remains in the write buffers, PI7C7100 initiates another write transaction to attempt to deliver the rest of the write data.
If there is a target retry, the exact same address will be driven as for the initial write transaction attempt. If a target
disconnect is received, the address that is driven on a subsequent write transaction attempt will be updated to reflect
the address of the current DWORD. If the initial write transaction is Memory-Write-and-Invalidate transaction, and a
partial delivery of write data to the target is performed before a target disconnect is received, PI7C7100 will use the
memory write command to deliver the rest of the write data. It is because an incomplete cache line will be transferred
in the subsequent write transaction attempt.
After the PI7C7100 makes 2²⁴(default) write transaction attempts and fails to deliver all posted write data associated with
that transaction, PI7C7100 asserts P_SERR# if the primary SERR# enable bit is set (bit 8 of command register for
secondary bus S1 or S2) and posted-write-non-delivery bit is not set. The posted-write-non-delivery bit is the bit 2 of
P_SERR# event disable register (offset 64h). PI7C7100 will report system error. See Section 7.4 for a discussion of system
error conditions.
4.8.3.3 Delayed Read Target Termination Response
When PI7C7100 initiates a delayed read transaction, the abnormal target responses can be passed back to the initiator.
Other target responses depend on how much data the initiator requests. Table 4–9 shows the response to each type
of target termination that occurs during a delayed read transaction.
PI7C7100 repeats a delayed read transaction until one of the following conditions is met:
• PI7C7100 completes at least one data transfer.
• PI7C7100 receives a master abort.
• PI7C7100 receives a target abort.
• PI7C7100 makes 2²⁴(default) read attempts resulting in a response of target retry.
Table 4-9. Responses to Delayed Read Target Termination
Target Termination
Response
Normal
If prefetchable, target disconnect only if initiator requests more data than read
from target. If non-prefetchable, target disconnect on first data phase.
Target retry
Reinitiate read transaction to target.
Target disconnect
If initiator requests more data than read from target, return target disconnect to
initiator.
Target abort
Return target abort to initiator. Set received target abort bit in the target interface
status register. Set signaled target abort bit in the initiator interface status
register.
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