PI6C49016 Datasheet, PDF (3/16 Pages) Pericom Semiconductor Corporation – Low Power Networking Clock Generator

PI6C49016
Low Power Networking Clock Generator
Pin List
Pin#
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin Name
X1
X2
VDDX
VDDO
125M
GND
VDD
66.66M
GND
VDD
GND
NC
VDD
GND
VDD
PCIE0N
PCIE0
PCIE1
PCIE1N
VDD
GND
VDD
Cdd
PCIE2N
PCIE2
Pin Type
XI
XO
Power
Power
Output
Power
Power
Output
Power
Power
Power
-
Power
Power
Power
Output
Output
Output
Output
Power
Power
Power
Input
Output
Output
Pin Description
Crystal input. Connect to 25 MHz fundamental mode
crystal or clock
Crystal output. Connect to 25 MHz fundamental
mode crystal. Float for clock input
3.3V Supply Pin
125 MHz output supply voltage. Connect to +2.5 V.
125 MHz, +2.5 V LVCMOS output. Tri-stated with a
weak pull-down when disabled.
Ground
3.3V Supply Pin
66.66 MHz LVCMOS output. Tri-stated with a weak
pull-down when disabled
Ground
3.3V Supply Pin
Ground
-
3.3V Supply Pin
Ground
3.3V Supply Pin
Differential 100 MHz PCI Express Clock output
Differential 100 MHz PCI Express Clock output
Differential 100 MHz PCI Express Clock output
Differential 100 MHz PCI Express Clock output
3.3V Supply Pin
Ground
3.3V Supply Pin
Input pin for off chip bypass capacitor. Connect to 0.01
μF capacitor
Differential 100 MHz PCI Express Clock output
Differential 100 MHz PCI Express Clock output
Notes: VDD and GND Pins Layout Guide
1. Small value decoupling caps. (0.1uF, 1uF, and 2.2uF) should be placed close each VDD pin or its via
2. Connect all GND pins to package thermal pad which must be connected to the GND plane for better thermal distribution and signal conducting with reasonable
via count (>8)
13-0102
3
www.pericom.com
PI6C49016
Rev. B
06/25/13