PI2EQX3431 Datasheet, PDF (3/5 Pages) Pericom Semiconductor Corporation – 3.2Gbps, 1-port, SATA2/SAS Re-Driver

PI2EQX3431
3.2 Gbps, 1-Port, SATA2 /SAS Re-Driver
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature........................................................ –65°C to +150°C
Supply Voltage to Ground Potential ................................... –0.5V to +2.5V
DC SIG Voltage.......................................................... –0.5V to V_CC +0.5V
Current Output ................................................................-25mA to +25mA
Power Dissipation Continous ......................................................... 500mW
Operating Temperature.............................................................. 0 to +70°C
Note:
Stresses greater than those listed under MAXIMUM RAT-
INGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
AC/DC Electrical Characteristics (V_DD = 1.8 ±0.1V)
Symbol
Parameter
Conditions
P_STANDBY
Supply Power
CE = LVCMOS Low
P_ACTIVE
Supply Power
CE = LVCMOS High
t_PD
Latency
From input to output
CML Receiver Input
V_RX-DIFFP-P
Differential Input Peak-to-
peak Voltage
V_RX-CM-ACP
AC Peak Common Mode
Input Voltage
Z_RX-DC
DC Input Impedance
Z_RX-DIFF-DC
DC Differential Input
Impedance
Min. Typ. Max. Units
0.1
W
0.3
1.0
ns
0.200
40 50
80 100
V
150 mV
60
Ohm
120
Equalization
J_RS
J_RM
Residual Jitter^(1,2)
Random Jitter^(1,2)
Signal Detector Performance
V_TH
Threshold
T_EN
Enable/disable time
Total Jitter
CE = 1
0.3 Ulp-p
1.5
psrms
75⁽³⁾
200 ⁽³⁾ mVppd
16
ns
Notes
1. K28.7 pattern is applied differentially at point A as shown in Figure 1.
2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 × RJ + DJ) where RJ is random RMS jitter and DJ is maximum
deterministic jitter. Signal source is a K28.5 ± pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or
equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or
its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. JItter is measured at
0V at point C of Figure 1.
3. Using Compliance test at 1.5Gbps and 3Gbps. Also using OOB (OOB is formed by ALIGNp primitive or D24.3) test patterns at 1.5Gbps. The
ALIGN primitive (K28.5+D10.2+D27.3 = 0011111010+0101010101+0010011100). The D24.3 = 00110011001100110011
08-0094
3
PS8960A
04/30/08