PT7A7511-15 Datasheet, PDF (2/9 Pages) Pericom Semiconductor Corporation – uP Supervisor Circuits

PT7A7511-15/7521-25/7531-35
μP Supervisor Circuits
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Pin Description
Pin
Type
Description
MR
I
Manual-Reset: triggers a reset pulse when pulled below 0.8V, active low. It has an internal 250mA pull-
up current and be driven from a TTL or CMOS logic line as well as shorted to ground with a switch.
V_CC
Power Supply Voltage.
GND Ground Ground Reference for all signals.
PFI
I
Power-Fail Voltage Monitor Input. When PFI is less than 1.25V, PFO goes low. Connect PFI to GND
or Vcc when not used.
PFO
O
Power-Fail Output: it gets low and sinks current when PFI is less than 1.25V; otherwise PFO stays high.
WDI
RESET
WDO
RESET
Watchdog Input: If WDI remains high or low for 1.6sec, the internal watchdog timer runs out and WDO
I
goes low. Floating WDI or connecting WDI to a high-impedance three-state buffer disables the watchdog
feature. The internal watchdog timer clears whenever reset is asserted. WDI is three-stated, or WDI sees a
rising or falling edge.
Reset Output pulses: low for 200ms when triggered, and stays low whenever Vcc is below the reset
O
threshold. It remains low for 200ms after Vcc rises above the reset threshold or MR goes from low to high.
A watchdog timeout will not trigger RESET unless WDO is connected to MR.
Watchdog Output: pulls low when the internal watchdog timer finishes its 1.6sec count and does not go
O
high again until the watchdog is cleared. WDO also goes low during low-line conditions. Whenever Vcc is
below the reset threshold, WDO stays low; however, unlike RESET, WDO does not have minimum pulse
width. As soon as Vcc rises above the reset threshold, WDO goes high with no delay.
O
The inverse of RESET, active high. Whenever RESET is high, RESET is low.
Block Diagram
Block Diagram of PT7A7511-7515/7521-7525
WDI
MR
Vcc
PFI
Watchdog
Transition Detector
Vcc
250uA
Watchdog Timer
Timebase for Reset
& Watchdog
Reset Generator
V_RST
1.25V
WDO
RESET
(RESET)
PFO
12-07-0002
PT0082-7
07/05/12
2