PI6LC48P02 Datasheet, PDF (2/11 Pages) Pericom Semiconductor Corporation – 2-Output LVPECL Fibre Channel (FC) and Ethernet Clock Generator

PI6LC48P02
2-Output LVPECL Fibre Channel (FC) and Ethernet Clock Generator
Pin Configuration
NC 1
VDDO 2
CLK0 3
CLK0# 4
M_reset ₅
PLL_ByPass ₆
NC 7
VDDA 8
N_SEL0 9
VDD 10
20 VDDO
19 CLK1
18 CLK1#
17 GND
16 VDD
15 IN_SEL
14 Ref_IN
13 XTAL_IN
12 XTAL_OUT
11 N_SEL1
Pinout Table
Pin No.
1, 7
2, 20
3,4
Pin Name
NC
VDDO
CLK0, CLK0#
I/O Type
Power
Output
5
M_reset
Input
6
8
9, 11
10, 16
12, 13
14
15
17
18, 19
PLL_ByPass
Input
VDDA
Power
N_SEL0, N_SEL1 Input
VDD
Power
XOUT, XIN
Crystal
Ref_IN
Input
IN_SEL
Input
GND
Ground
CLK1#,
CLK1
Output
Description
No connection
-
Output Power Supply
-
LVPECL Output clock 0
Pull-down
Master reset. “1”, CLK0/CLK1 go to “low”, CLK0#/CLK1# go to
“high”; “0” outputs are enabled
Pull-down PLL bypass select. “0” PLL is enabled, “1” PLL is bypassed
-
Analog Power Supply
Pull-down Output frequency select
-
Core Power Supply
-
Crystal input and output
Pull-down CMOS reference clock input
Pull-down “0” selects Crystal, “1” selects reference input
-
Ground
-
LVPECL Output clock 1
15-0102
2
www.pericom.com
PI6LC48P02
Rev. C
08/13/15