PI6C2510-133 Datasheet, PDF (2/5 Pages) Pericom Semiconductor Corporation – Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs

PI6C2510-133
Low-Noise, Phase-Locked Loop
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Pin Functions
Pin Name Pin Number
CLK_IN
24
FB_IN
13
G
11
FB_OUT
12
Y[0:9]
3,4,5,8,9,15
16,17,20,21
AV_CC
23
Type
I
I
I
O
O
Power
Description
Reference Clock input. CLK_IN allows spread spectrum.
Feedback input. FB_IN provides the feedback signal to the internal PLL
Output bank enable. When G is LOW, outputs Y[0:9] are disabled to
a logic low state. When G is HIGH, all outputs Y[0:9] are enabled.
Feedback output. FB_OUT is dedicated for external feedback.
FB_OUT has an embedded series-damping resistor of the same
value as the clock outputs Y[0:9].
Clock outputs. These outputs provide low-skew copies of
CLK_IN_. Each output has an embedded series-damping resistor.
Analog power supply. AV_CC can be also used to bypass the PLL for
test purposes. When AV_CC is strapped to ground, PLL is bypassed and
CLK_IN buffered directly to the device outputs.
AGND
1
Ground Analog ground. AGND provides the ground reference for the analog circuitry.
V_CC
2,10,14,22
Power Power supply
GND
6,7,18,19
Ground Ground
2
PS8383B 09/14/04