PI7C8150B Datasheet, PDF (13/108 Pages) Pericom Semiconductor Corporation – ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Name
P_IRDY_L
Pin #
82
P_TRDY_L
83
P_DEVSEL_L
84
P_STOP_L
85
P_LOCK_L
87
P_IDSEL
65
P_PERR_L
88
P_SERR_L
89
P_REQ_L
47
P_GNT_L
46
P_RESET_L
43
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
Pin #
T10
R10
P10
T11
R11
P6
T12
P11
P2
R1
P1
Type
STS
STS
STS
STS
STS
I
STS
OD
TS
I
I
Description
Primary IRDY (Active LOW). Driven by the initiator
of a transaction to indicate its ability to complete current
data phase on the primary side. Once asserted in a data
phase, it is not de-asserted until the end of the data
phase. Before tri-stated, it is driven to a de-asserted
state for one cycle.
Primary TRDY (Active LOW). Driven by the target
of a transaction to indicate its ability to complete current
data phase on the primary side. Once asserted in a data
phase, it is not de-asserted until the end of the data
phase. Before tri-stated, it is driven to a de-asserted state
for one cycle.
Primary Device Select (Active LOW). Asserted by the
target indicating that the device is accepting the
transaction. As a master, PI7C8150B waits for the
assertion of this signal within 5 cycles of P_FRAME_L
assertion; otherwise, terminate with master abort. Before
tri-stated, it is driven to a de-asserted state for one cycle.
Primary STOP (Active LOW). Asserted by the target
indicating that the target is requesting the initiator to
stop the current transaction. Before tri-stated, it is driven
to a de-asserted state for one cycle.
Primary LOCK (Active LOW). Asserted by the
master for multiple transactions to complete.
Primary ID Select. Used as a chip select line for Type
0 configuration access to PI7C8150B configuration
space.
Primary Parity Error (Active LOW). Asserted when
a data parity error is detected for data received on the
primary interface. Before being tri-stated, it is driven to
a de-asserted state for one cycle.
Primary System Error (Active LOW). Can be driven
LOW by any device to indicate a system error condition.
PI7C8150B drives this pin on:
Address parity error
Posted write data parity error on target bus
Secondary S_SERR_L asserted
Master abort during posted write transaction
Target abort during posted write transaction
Posted write transaction discarded
Delayed write request discarded
Delayed read request discarded
Delayed transaction master timeout
This signal requires an external pull-up resistor for
proper operation.
Primary Request (Active LOW): This is asserted by
PI7C8150B to indicate that it wants to start a transaction
on the primary bus. PI7C8150B de-asserts this pin for at
least 2 PCI clock cycles before asserting it again.
Primary Grant (Active LOW): When asserted,
PI7C8150B can access the primary bus. During idle and
P_GNT_L asserted, PI7C8150B will drive P_AD,
P_CBE, and P_PAR to valid logic levels.
Primary RESET (Active LOW): When P_RESET_L is
active, all PCI signals should be asynchronously tri-
stated.
06-0044
Page 13 of 108
APRIL 2006 – Revision 2.02