PT7C4337_13 Datasheet, PDF (10/23 Pages) Pericom Semiconductor Corporation – Real-time Clock Module

PT7C4337
Real-time Clock Module (I²C Bus)
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Square wave frequency selection bits
 RS2, RS1
Square wave Rate Select. These bits control the frequency of the square-wave output when the square wave has been enabled.
RS2, RS1
Data
SQW output freq. (Hz)
00 1
Read / Write
01 4.096k
10 8.192k
11 32.768k
Default
Interrupt related bits
 INTCN
Interrupt Output pin select bit. This bit controls the relationship between the two alarms and the interrupt output pins.
INTCN Data
Description
Read /
Write
A match between the timekeeping registers and the alarm 1 registers activates the INTA pin (if the
1 alarm 1 is enabled) and a match between the timekeeping registers and the alarm 2 registers activates
the SQW/INTB pin (if the alarm 2 is enabled).
A match between the timekeeping registers and either alarm 1 or alarm 2 registers activates
Default
0 the INTA pin (if the alarms are enabled). In this configuration, a square wave is output on
the SQW/INTB pin.
 A1IE
A1IE
Read /
Write
Alarm 1 Interrupt Enable.
Data
Description
0 The A1F bit does not initiate the INTA signal.
1 Permits the alarm 1 flag (A1F) bit in the status register to assert INTA.
Default
 A1F
A1F
Data
Read / Write 0
Read
1
Alarm 1 Flag.
Description
The time do not match the alarm 1 registers.
Default
Indicates that the time matched the alarm 1 registers. If the A1IE bit is also logic 1, the INTA pin goes
low. A1F is cleared when written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
 A2IE
Alarm 2 Interrupt Enable.
A2IE
Data
Description
Read /
Write
0 The A2F bit does not initiate an interrupt signal.
Default
Permits the alarm 2 flag (A2F) bit in the status register to assert INTA (when INTCN = 0) or to assert
1
SQW/INTB (when INTCN = 1).
2013-06-0002
PT0205-9 06/18/13
10