PI6C5922504 Datasheet, PDF (10/12 Pages) Pericom Semiconductor Corporation – 2.5 GHz 1:4 LVDS Fanout Buffer with Internal Termination

PI6C5922504
2.5 GHz 1:4 LVDS Fanout Buffer with Internal Termination
LVPECL Output V_swing Adjustment
It is suggested to add another cross 100ohm at TX side to tune
the LVPECL output V_swing without changing the optimal
150ohm pull-down bias in Fig. 12. This form of double termina-
tion can reduce the V_swing in ½ of the original at the RX side.
By fine tuning the 100ohm resistor at the TX side with larger
values like 150 to 200ohm, one can increase the V_swing by >
1/2 ratio.
Device Thermal Calculation
Fig. 13 shows the JEDEC thermal model in a 4-layer PCB.
Fig. 13 JEDEC IC Thermal Model
Fig. 12 LVPECL Output V_swing Adjustment
Clock Jitter Definitions
Total jitter= RJ + DJ
Random Jitter (RJ) is unpredictable and unbounded timing noise
that can fit in a Gaussian math distribution in RMS. RJ test val-
ues are directly related with how long or how many test samples
are available. Deterministic Jitter (DJ) is timing jitter that is pre-
dictable and periodic in fixed interference frequency. Total Jitter
(TJ) is the combination of random jitter and deterministic jitter:
, where is a factor based on total test sample count. JEDEC std.
specifies digital clock TJ in 10k random samples.
Phase Jitter
Phase noise is short-term random noise attached on the clock
carrier and it is a function of the clock offset from the car-
rier, for example dBc/Hz@10kHz which is phase noise power
in 1-Hz normalized bandwidth vs. the carrier power @10kHz
offset. Integration of phase noise in plot over a given frequency
band yields RMS phase jitter, for example, to specify phase jitter
<=1ps at 12k to 20MHz offset band as SONET standard specifi-
cation.
Important factors to influence device operating temperature are:
1) The power dissipation from the chip (P_chip) is after subtract-
ing power dissipation from external loads. Generally it can be
the no-load device Idd
2) Package type and PCB stack-up structure, for example, 1oz
4 layer board. PCB with more layers and are thicker has better
heat dissipation
3) Chassis air flow and cooling mechanism. More air flow M/s
and adding heat sink on device can reduce device final die junc-
tion temperature Tj
The individual device thermal calculation formula:
Tj =Ta + Pchip x Ja
Tc = Tj - Pchip x Jc
Ja ___ Package thermal resistance from die to the ambient air
in C/W unit; This data is provided in JEDEC model simulation.
An air flow of 1m/s will reduce Ja (still air) by 20~30%
Jc ___ Package thermal resistance from die to the package case
in C/W unit
Tj ___ Die junction temperature in C (industry limit <125C
max.)
Ta ___ Ambiant air température in C
Tc ___ Package case temperature in C
Pchip___ IC actually consumes power through Iee/GND cur-
rent
14-0127
10
PI6C5922504 Rev A
08/14/2014