PT7C4511 Datasheet, PDF (1/5 Pages) Pericom Semiconductor Corporation – PLL Clock Multiplier

PT7C4511
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PLL Clock Multiplier
Features
Description
 Zero ppm multiplication error
The PT7C4511 is a high performance frequency
 Input crystal frequency of 5 - 30 MHz
multiplier, which integrates Analog Phase Lock Loop
 Input clock frequency of 1 - 50 MHz
techniques.
 Output clock frequencies up to 200 MHz
 Peak to Peak Jitter less than 200ps over 200ns
interval (100~200MHz)
 Low period jitter 50ps (100~200MHz)
 9 selectable frequencies controlled by S0, S1 pins
 Operating voltages of 3.0 to 5.5V
 Tri-state output for board level testing
 Lead free SOIC-8 package
The PT7C4511 is the most cost effective way to
generate a high quality, high frequency clock output
from a lower frequency crystal or clock input. It is
designed to replace crystal oscillators in most electronic
systems, clock multiplier and frequency translation.
Using Phase-Locked-Loop (PLL) techniques, the device
uses a standard fundamental mode, inexpensive crystal
to produce output clocks up to 200 MHz.
The complex Logic divider is the ability to generate nine
Pin Configuration
different popular multiplication factors, allowing one
chip to output many common frequencies.
1 X1/ICLK X2 8
2 Vcc
OE 7
3 GND
S0 6
4 S1
CLK 5
The device also has an Output Enable pin that tri-states
the clock output when the OE pin is taken low. This
product is intended for clock generation and frequency
translation with low output jitter (variation in the output
period).
SOIC-8 package
Pin Description
Name
X1/ICLK
Vcc
GND
S1
CLK
S0
OE
X2
Pin No.
1
2
3
4
5
6
7
8
Type
X1
P
P
T1
O
T1
I
XO
Description
Crystal connection or clock input.
Connect to +3.3V or +5V.
Connect to ground.
Multiplier select pin, connect to
GND or Vcc or floating (no
connection).
Clock output per Table below.
Multiplier select pin 0, connect to
GND or Vcc or floating (no
connection).
Output enable, tri-state CLK
output when low. Internal pull-up.
Crystal connection. Leave
unconnected for clock input.
Clock Output Table
S1
S0
CLK
0
0
×4
0
M
×(16/3)
0
1
×5
M
0
×2.5
M
M
×2
M
1
×(10/3)
1
0
×6
1
M
×3
1
1
×8
1) Note: CLK output frequency=ICLK×4.
2) Note: M=Leave unconnected (self-biases to
Vcc/2).
2014-08-0004
PT0138-5
08/14/14
1