PI90LVB16 Datasheet, PDF (1/12 Pages) Pericom Semiconductor Corporation – 3V Bus LVDS 1-to-6 Clock Buffer/Bus Transceiver

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3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
Features
General Description
• Master/Slave clock selection in a backplane application
• 160 MHz operation (typical)
• 100ps duty cycle distortion (typical)
• 50ps channel to channel skew (typical)
• 3.3V power supply design
• Glitch-free power on at CLKI/O pins
• Low Power design (16mA @ 3.3V static)
• Accepts small swing (300mV typical) differential signal levels
• Industrial temperature operating range (–40°C to +85°C)
• Available in 24-pin TSSOP Packaging (L)
PI90LVB16 is a six-channel LVTTL clock distribution driver with 50
picosecond channel-to-channel skew. It translates one BLVDS
(Bus Low-Voltage Differential Signaling) input signal into six LVTTL-
compatible output signals for distribution to adjacent chips on the
same board. The PI90LVB16 accepts BLVDS (300mV typical) differ-
ential input levels, and translates them to 3V CMOS output levels.
The 160MHz PI90LVB16 can be the master clock, driving inputs of
other clock I/O pins in a multipoint environment. It can also drive
the BLVDS backplane with a separate channel acting as a return/
source LVTTL clock source. The master/slave clock selection of the
driving source is controlled by the CrdCLK_IN and the DE pins. An
output enable pin OE, when high, forces all CLK_OUT pins high.
A backplane clock distribution network must be able to drive many
transmission line stubs. The Bus LVDS feature of the PI90LVB16 is
ideal for driving data transfers in large, high-performance backplane
system applications. The device can be used as a source synchro-
nous driver to distribute clock signals within data and telecommu-
nications systems.
Driver Mode Truth Table
Input
OE DE CrdCLK_IN CLKI/O+
LL
L
L
LL
H
H
HL
L
L
HL
H
H
HH
X
Z
Output
CLKI/O–
H
L
H
L
Z
CLK_OUT
L
H
H
H
H
Receive Mode Truth Table
Input
Output
OE DE CrdCLK_IN (CLKI/O+)–(CLKI/O–) CLK_OUT
HH
X
X
H
LH
X
VID ≥ 0.07V
H
LH
X
VID ≤ –0.07V
L
L = Low Logic State; H = High Logic State; X = Irrelevant
Z = High Impedance
Function Diagram
OE
CLKI/0+
CLKI/0–
R
D
Delay
MUX
CLK_OUT0
CLK_OUT1
CLK_OUT5
DE
CrdCLK_IN
1
PS8536A 05/21/01