PI90LVB010 Datasheet, PDF (1/9 Pages) Pericom Semiconductor Corporation – Single Bus LVDS Transceiver

PI90LVB010
Single Bus LVDS Transceiver
Features
• Bus LVDS Signaling (BLVDS)
• Designed for Double Termination Applications
• Balanced Output Impedance
• Light Bus Loading: 5pF typical
• Glitch-free power up/down (Driver Disabled)
• Operates from a 3.3V supply
• High Signaling Rate Capability: >100Mbps
• Driver:
– ±250mV Differential Swing into a 27Ω load
– Propagation Delay of 1.5ns typ.
– Low Voltage TTL (LVTTL) Inputs are 5V Tolerant
– Driver is High Impedance when disabled or V_CC <1.5V
• Receiver:
– Accepts ±50mV (min.) Differential Swing with up to 2.0V
ground potential difference
– Propagation Delay of 3.3ns typical
– Low Voltage TTL (LVTTL) Outputs
– Open, Short, and Terminated Fail Safe
• Bus terminal ESD exceeds 10kV
• Industrial Temperature Operation (–40°C to +85°C)
• Packaging (Pb-free & Green available):
– 8-lead SOIC (W)
– 8-lead MSOP (U)
Description
The PI90LVB010 is a differential line driver and receiver (trans-
ceiver) that is similar to the IEEE1596.3 SCI and ANSI/TIA/EIA-
644LVDS standards, the difference is that the driver output current
is higher. This modification enables true half-duplex operation with
more than one LVDS driver or with two line transmission resistors
over a 50Ω differential transmission line. To minimize bus loading,
the driver outputs and receiver inputs are internally connected. The
logic interface provides maximum flexibility resulting from four
separate lines that are provided: D_IN, DE, RE, and R_OUT.
This device also feature flow-through which allows easy PCB
routing for short stubs between the bus pins and the connector.
The driver has 10mA drive capability, allowing it to drive heavily
loaded backplanes, with impedance as low as 27Ω.
The driver translates between TTL levels (single-ended) to Low
Voltage Differential Signaling levels. This allows for high-speed
operation, while consuming minimal power with reduced EMI. In
addition the differential signaling provides common mode noise
rejection of ±1V.
Block Diagram
DIN
DE
RE
ROUT
D0+/RI+
D0–/RI–
Pin Configuration
DE 1
D_IN 2
R_OUT 3
GND 4
8 VCC
7 DO+/RI+
6 DO–/RI–
5 RE
1
PS8662A
09/03/04