PI90LV386 Datasheet, PDF (1/8 Pages) Pericom Semiconductor Corporation – High-Speed Differential Line Receivers

PI90LV386/PI90LVT386
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High-Speed Differential Line Receivers
Features
• Sixteen line receivers meet or exceed the requirements of the
ANSI TIA/EIA-644-1995 Standard
• Designed for signaling rates up to 660 Mbps
• 0V to 3V common-mode input voltage range
• Operates from a single 3.3V supply
• Typical propagation delay time: 2.6ns
• Output skew 100ps (typical)
• Part-to-part skew is less than 1ns
• Integrated 110-Ohm termination on PI90LVT386
• Low Voltage TTL (LVTTL) levels are 5V tolerant
• Open-circuit fail safe
• Flow-through pin out
• Packaging (Pb-free & Green available):
- 64-Pin Thin Shrink Small Output TSSOP (A)
Pin Configuration
Description
The PI90LVx386 family consists of sixteen differential line receivers
with 3-state outputs that implement Low-Voltage Differential
Signaling (LVDS). Any of the differential receivers will provide a
valid logical output state with a ±100mV differential input voltage
within the input common-mode voltage range that allows 0 to 3V of
ground potential difference between two LVDS nodes. The indepen-
dent EN pins can be used to place the outputs in either a normal logic
state (high or low logic levels) or a high-impedance state. In high-
impedance state, outputs neither load nor drive the bus lines.
The intended application of these devices, and their signaling
techniques, is for point-to-point baseband data transmission over
controlled impedance media of approximately 100-ohms with a
100-Ohm termination resistor. The PI90LVT386 integrates the termi-
nating resistors while the PI90LV386 requires external resistors.
The transmission media may be printed circuit board traces,
backplanes, or cables. The PI90LV386’s 16 receivers integrated into
the same substrate allow precise timing alignment.
These parts are characterized for operation from –40°C to 85°C.
1RIN1+
1RIN1–
1RIN2+
1RIN2–
1RIN3+
1RIN3–
1RIN4+
1RIN4–
2RIN1+
2RIN1–
2RIN2–
2RIN2–
2RIN3+
2RIN3–
2RIN4+
2RIN4–
3RIN1+
3RIN1–
3RIN2+
3RIN2–
3RIN3+
3RIN3–
3RIN4+
3RIN4–
4RIN1+
4RIN1–
4RIN2+
4RIN2–
4RIN3+
4RIN3–
4RIN4+
4RIN4–
1
64
2
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
11
54
12
53
13
52
14 _64-Pin 51
15
A ⁵⁰
16
49
17
48
18
47
19
46
20
45
21
44
22
43
23
42
24
41
25
40
26
39
27
38
28
37
29
36
30
35
31
34
32
33
GND
VCC
VCC
GND
EN1
1ROUT1
1ROUT2
1ROUT3
1ROUT4
EN2
2ROUT1
2ROUT2
2ROUT3
2ROUT4
GND
VCC
VCC
GND
3ROUT1
3ROUT2
3ROUT3
3ROUT4
EN3
4ROUT1
4ROUT2
4ROUT3
4ROUT4
EN4
GND
VCC
VCC
GND
Block Diagram
16 Receivers
1
PS8574B
10/04/04