PI90LV211 Datasheet, PDF (1/9 Pages) Pericom Semiconductor Corporation – 1:6 Differential Clock Distribution Chip

PI90LV211/PI90LVT211
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1:6 Differential Clock Distribution Chip
Features
Description
• Meets or Exceeds Requirements of ANSI TIA/EIA-644-1995
• Designed for Clocking Rates up to 320MHz
• Operates from a single 3.3-V Supply
• Low-Voltage Differential Signaling (LVDS) with Output
Voltages of ±350mV into a 100-ohm load
• Choice between LVDS or TTL clock input
• Synchronous Enable/Disable
• Multiplexed clock input
– Internal 300 kohm pullup resistor on all control pins
– CLK and CLK have 110-ohm termination (PI90LVT211)
• Common and individual Enable/Disable control
• 50ps Output-to-Output Skew
• ±24ps Period Jitter
• Bus Pins are High Impedance when disabled or with V_CC <1.5V
• TTL Inputs are 5V Tolerant
• Power Dissipation at 300 MHz
• P190LV211 is functionally compatible with Motorola’s
(PECL) MC 10E211/MC100E211
• >12kV ESD Protection
• Packaging (Pb-free & Green available):
- 28-pin TSSOP (L)
- 28-pin QSOP (Q)
The PI90LV211 implements low voltage differential signaling (LVDS)
to achieve clocking rates as high as 320 MHz with low skew. The
PI90LV211 is a low skew 1:6 fanout device designed explicitly for low
skew clock distribution applications. The device features a multi-
plexed clock input to allow for the distribution of a lower speed scan
or test clock with the high-speed system clock. When LOW the SEL
pin will select the differential clock input.
Both a common enable and individual output enables are provided.
When asserted the positive output will go LOW on the next negative
transition of the CLK (or SCLK) input. The enable function is
synchronous so that the outputs will only be enabled/disabled when
they are already in the LOW state. This avoids any chance of
generating a runt clock pulse when the device is enabled/disabled
as can happen with an asynchronous control. The internal flip flop
is clocked on the falling edge of the input clock, therefore all
associated specification limits are referenced to the negative edge
of the clock input.
Individual synchronous enable controls and multiplexed clock in-
puts make this device ideal as the first level distribution unit in a
distribution tree. The individual enables could be used to allow for the
disabling of individual cards on a backplane in fault tolerant designs.
Function Table
Block Diagram & Pin Configuration
CLK/CLK SCLK SEL ENx CEN CLK OUT (±)
V_CC 1
EN1 ²
GND 3
EN2 ⁴
5
SCLK
1
CLK ⁶
PI90LVT211
Only ^110Ω
CLK ⁷
0
EN3 ⁸
SEL ⁹
10
EN4
11
EN5
12
EN6
13
CEN
GND 14
H/L
X
L
L
L
CLK
X
H/L H
L
L
SCLK
D
28
V_CC
27
CLK1_OUT+
↓
↓
X
H
L
Z*
26
CLK1_OUT–
↓
↓
H
L
H
Z**
Q
D
25
CLK2_OUT+
* ENx disables individual banks
Q
24
CLK2_OUT–
** CEN disables all six banks
↓ = Negative transition of CLK or SCLK
Z = High Impedance
D
23
CLK3_OUT+
22
CLK3_OUT–
Q
D
21
CLK4_OUT+
20
CLK4_OUT–
Q
D
19
CLK5_OUT+
18
CLK5_OUT–
Q
D
17
CLK6_OUT+
16
CLK6_OUT–
Q
15 GND
1
PS8535C 10/04/04