PI90LV14 Datasheet, PDF (1/6 Pages) Pericom Semiconductor Corporation – 1:5 Clock Distribution

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1:5 Clock Distribution
Features
• Meets and Exceeds the Requirements of ANSI
TIA/EIA-644-1995
• Designed for clocking rates up to 320MHz
• Operates from a single 3.3V Supply
• Low Voltage Differential Signaling (LVDS) with Output
Voltages of ±350mV into a 100Ωload
• Choice between LVDS or TTL clock input
• Synchronous Enable/Disable
• Clock outputs default LOW when inputs open
• Multiplexed clock input
- Internal 300kΩ pullup resistor on input pins
- CLK and CLK have 110Ωinternal termination (PI90LVT14)
• 50ps Output-to-Output Skew
• 475ps typical propagation delay
• Bus Pins are high impedance when disabled or with
V_CC less than 1.5V
• TTL inputs are 5V Tolerant
• Power Dissipation at 400Mbits/s of 150mW
• Function compatible to Motorola (PECL)
MC100EL14 and Micrel/Synergy (PECL)
SY100EL14V
• >9kV ESD Protection
• 20-pin TSSOP (L) and QSOP (Q) packages
Pin Descriptions
Pin
Funtion
CLK, CLK
Differential Clock Outputs
SCLK
LVTTL Clock Input
EN
Synchronous Enable
SEL
Clock Select Input
CLK1-5_OUT±
Differential Clock Inputs
Function Table
CLK SCLK SEL
EN* CLKOUT+
L
X
L
L
L
H
X
L
L
H
X
L
H
L
L
X
H
H
L
H
↓
↓
X
H
Z*
* On next negative transition of CLK, or SCLK
Description
The PI90LV14 implements low voltage differential signaling (LVDS)
to achieve clocking rates as high as 320MHz with low skew.
The PI90LV14 is a low-skew 1:5 clock distribution chip which
incorporates multiplexed clock inputs to allow for distribution of a
lower-speed, single-ended clock or a high-speed system clock.
When LOWthe SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the outputs will
only be enabled/disabled when they are already in the LOW state.
This avoids any chance of generating a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. Because the internal flip-flop is clocked on the falling edge
of the input clock, all associated specification limits are referenced
to the negative edge of the clock input.
The intended application of these devices and signaling technique
is for high-speed clock distribution between boards.
PI90LV14 Block Diagram
CLK1_OUT+
1
2
CLK1_OUT–
CLK2_OUT+
3
4
CLK2_OUT–
CLK3_OUT+
5
CLK3_OUT–
6
CLK4_OUT+
7
8
CLK4_OUT–
CLK5_OUT+
9
10
CLK5_OUT–
D
Q
20 VCC
19
EN
18 VCC
17 GND
1
16 _SCLK
15
CLK
110Ω
PI90LVT14
0
Only ₁₄
CLK
13 GND
12 SEL
11 GND
1
PS8538
04/25/01