PI90LV048A Datasheet, PDF (1/7 Pages) Pericom Semiconductor Corporation – 3V LVDS Quad Flow-Through Differential Line Receivers

PI90LV048A/PI90LVT048A
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3V LVDS Quad Flow-Through
Differential Line Receivers
Features
• 500 Mbps (250 MHz) switching rates
• Flow-through pinout simplifies PCB layout
• 150ps channel-to-channel skew (typical)
• 100ps differential skew (typical)
• 2.7ns maximum propagation delay
• 3.3V power supply design
• High impedance LVDS inputs on power down
• Low Power design (40mW, 3.3V static)
• Wide common-mode input voltage range: 0.2V to 2.7V
• Accepts small swing (350mV typical) differential signal levels
• Supports open, short and terminated input fail-safe
• Low-power state when in fail-safe
• Conforms to ANSI/TIA/EIA-644 Standard
• Industrial temperature operating range (–40°C to +85°C)
• Packaging (Pb-free & Green available):
- 16-pin SOIC (W)
- 16-pin TSSOP (L)
Block Diagram
R_IN1+
4 Places
PI90LVT048A
100Ω
R1
Only
R_IN1–
ROUT1
R_IN2+
R2
R_IN2–
ROUT2
R_IN3+
R3
R_IN3–
ROUT3
R_IN4+
R4
R_IN4–
ROUT4
EN
EN
Description
The PI90LV048A/PI90LVT048A quad flow-through differential line
receivers are designed for applications requiring ultra low-power
dissipation and high data rates. The device is designed to support
data rates in excess of 500 Mbps (250 MHz) using Low Voltage
Differential Signaling (LVDS) technology.
The devices accept low-voltage (350 mV typical) differential input
signals and translates them to 3V CMOS output levels. The receiver
supports a 3-state function, which may be used to multiplex outputs,
and also supports open, shorted and terminated (100-ohms) input fail-
safe. The receiver output will be HIGH for all fail-safe conditions.
PI90LVT048A features integrated parallel termination resistors
(nominally 110-ohms) that eliminate the requirement for four dis-
crete termination resistors and reduce stud length. PI90LV048A
inputs are high impedance and require an external termination
resistor when used in a point-to-point connection. The devices
have a flow-through pinout for easy PCB layout.
The EN and EN inputs are ANDed together and control the 3-state
outputs. The enables are common to all four receivers. The
PI90LV048A and companion LVDS line driver (eg. PI90LV047A)
provide a new alternative to high-power PECL/ECL devices for
high-speed point-to-point interface applications.
Pin Configuration
R_IN1–
1
R_IN1+
2
R_IN2+
3
R_IN2–
4
R_IN3–
5
R_IN3+
6
R_IN4+
7
R_IN4–
8
16
EN
15
R_OUT1
14
R_OUT2
13
V_CC
12
GND
11
R_OUT3
10
R_OUT4
9
EN
Truth Table
Enables
EN
EN
H
L or Open
All other combinations of ENABLE inputs
Inputs
R_IN+ – R_IN–
V_ID ≥ 0.1V
V_ID ≤ –0.1V
Full fail-safe OPEN/SHORT or terminated
X
Outputs
R_OUT
H
L
H
Z
1
PS8608A
10/04/04