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PI90LV024 Datasheet, PDF (1/12 Pages) Pericom Semiconductor Corporation – LVDS Dual 2x2 Crosspoint/Repeater Switch
PI90LV024, PI90LVB024
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LVDS Dual 2x2 Crosspoint/Repeater Switch
Features
• Dual 2x2 Crosspoint/Repeater Switch
• Meets or Exceeds the Requirements of ANSI TIA/
EIA-644-1995
• Designed for Signaling Rates up to 650 Mbit/s (325 MHz)
• Operates from a 3.3V Supply: –40°C to 85°C
• Low Voltage Differential Signaling with Output Voltages
of ±350mV into:
– 100 Ohm load (PI90LV024)
–50 Ohm load Bus LVDS Signaling (PI90LVB024)
• Accepts ±350mV differential inputs
• Wide common mode input range: 0.2V to 2.7V
• Output drivers are high impedance when disabled or when
VCC ≤1.5V
• Inputs are open, short, and terminated fail safe
• Propagation Delay Time: 3.5ns
• ESD protection is 10kV on bus pins
• Bus Pins are High Impedance when disabled or with
VCC less than 1.5V
• TTL Inputs are 5V Tolerant
• Power Dissipation at 400Mbit/s of 250mW
• Available Packaging: 28-pin QSOP, 28-pin TSSOP
Description
The PI90LV024 and PI90LVB024 are monolithic dual 2x2 asynch-
ronous crosspoint/repeater switches. The crosspoint function is
based on a multiplexer tree architecture. Each 2x2 switch can be
considered as a pair of 2:1 multiplexers that share the same inputs.
The signal path through each switch is fully differential with minimal
propagation delay. The signal path is unregistered, so no clock is
required for the data inputs. The signal line drivers and receivers use
Low Voltage Differential Signaling (LVDS) to achieve signaling
rates as high as 650 Mbps.
The LVDS standard provides a minimum differential output voltage
magnitude of 247mV into a 100 Ohm load and receipt of 100mV
signals with up to 1V of ground potential difference between a
transmitter and receiver. The PI90LVB024 doubles the output drive
current to achieve Bus LVDS signaling levels with a 50 Ohm load.
The intended application of these devices is for loop-through and
redundant channel switching for both point-to-point base-band
(PI90LV024) and multipoint (PI90LVB024) data transmissions over
controlled impedance media. The package pin assignments enables
easy routing for applications requiring signal feedback.
Block Diagram
S0/S1
1A/1B
2A/2B
3Y/3Z
4Y/4Z
3DE/4DE
Pin Configuration
1DE/2DE
1Y/1Z
2Y/2Z
3A/3B
4A/4B
S2/S3
1B
1A
S0
1DE
S1
2A
2B
GND
4Y
4Z
4DE
3Z
3Y
VCC
1
28
2
27
3
26
4
25
5 28-Pin 24
6 L,Q 23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
1Y
1Z
2DE
2Z
2Y
GND
4B
4A
S3
3DE
S2
3A
3B
1
PS8486A 03/27/01
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