PI90LV022 Datasheet, PDF (1/12 Pages) Pericom Semiconductor Corporation – LVDS Mux/Repeater

PI90LV022, PI90LVB022
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LVDS Mux/Repeater
Features
• Meets or Exceeds the Requirements of ANSI TIA/
EIA-644-1995
• Designed for Signaling Rates up to 650 Mbit/s (325 MHz)
• Operates from a 3.3V Supply: –40°C to +85°C
• Low Voltage Differential Signaling with Output Voltages
of ±350mV into:
- 100 Ohm load (PI90LV022)
- 50 Ohm load Bus LVDS Signaling (PI90LVB022)
• Accepts ±350mV differential inputs
• Wide common mode input voltage range: 0.2V to 2.7V
• Output drivers are high impedance when disabled or
when V_CC ≤ 1.5V
• Inputs are open, short, and terminated fail safe
• Propagation Delay Time: 3.5ns
• ESD protection is 10kV on bus pins
• Bus Pins are High Impedance when disabled or
with V_CC less than 1.5V
• TTL Inputs are 5V I/O Tolerant
• Power Dissipation at 400Mbit/s less than 150mW
• Industrial temperature rating
• Packaging (Pb-free & Green available):
- 16-pin SOIC (W)
- 16-pin TSSOP (L)
Block Diagram
Description
The PI90LV022 and PI90LVB022 are differential line drivers and
receivers that use Low Voltage Differential Signaling (LVDS) to
achieve signaling rates as high as 650 Mbps. The receiver outputs
can be switched to either or both drivers through the multiplexer
control signals S0 and S1. This allows the flexibility to perform
splitter or signal routing functions with a single device.
The LVDS standard provides a minimum differential output voltage
magnitude of 247mV into a 100 Ohm load and receipt of 100mV DC
signals with up to 1V of ground potential difference between a
transmitter and receiver. The PI90LVB022 doubles the output drive
current to achieve Bus LVDS signaling levels with a 50 Ohm load.
A doubly terminated Bus LVDS line enables multi-point configura-
tions. Switching between channels does not create false transitions
on the outputs.
The intended application of these devices and signaling technique
is for both point-to-point base-band (PI90LV022) and multipoint
(PI90LVB022) data transmissions over controlled impedance media.
Pin Configuration
1DE
1A +
1Y
1B –
1Z
2A +
2Y
2B –
2Z
2DE
S0 S1
1B
1A
S0
1DE
S1
2A
2B
GND
1
16
2
15
3
14
16-Pin
4 _L,W 13
5
12
6
11
7
10
8
9
V_CC
V_CC
1Y
1Z
2DE
2Z
2Y
GND
1
PS8488B
09/28/04