PI74SSTVF16859 Datasheet, PDF (1/8 Pages) Pericom Semiconductor Corporation – 13-Bit to 26-Bit Registered Buffer

PI74SSTVF16859
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13-Bit to 26-Bit Registered Buffer
Product Features
Product Description
• PI74 SSTVF16859 is designed for low-voltage operation,
2.5V for PC1600 ~ PC2700; 2.6V for PC3200
• Supports SSTL_2 Class I specifications on outputs
• All Inputs are SSTL_2 Compatible, except RESET
which is LVCMOS.
• Designed for DDR Memory
• Flow-Through Architecture
• Packages:
64-pin, 240-mil wide plastic TSSOP (A)
56-pin, Plastic Very Thin Fine Pitch Quad Flat
No Lead QFN (ZB)
Logic Block Diagram - TSSOP
48
CLK
49
CLK
RESET ⁵¹
35
D1
45
V_REF
R
CLK
D
16 _Q1A
32 _Q1B
TO 12 OTHER CHANNELS
Logic Block Diagram - QFN
35
CLK
36
CLK
RESET ³⁸
24
D1
32
V_REF
R
CLK
D
7 _Q1A
22 _Q1B
Pericom Semiconductor’s PI74SSTVF16859 logic circuit is produced
using the Company’s advanced sub-micron CMOS technology,
achieving industry leading speed.
All inputs are compatible with the JEDEC standard for SSTL_2,
except the LVCMOS reset (RESET) input. All outputs are SSTL_2,
Class II compatible.
The device operates from a differential clock (CLK and CLK). Data
registered at the crossing of CLK going HIGH, and CLK going LOW.
The PI74SSTVF16859 supports low-power standby operation. When
RESET is LOW, the differential input receivers are disabled, and
undriven (floating) data, clock and reference voltage (V_REF) inputs
are allowed. In addition, when RESET is LOW, all registers are reset,
and all outputs are forced LOW. The LVCMOS RESET input must
always be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock
has been supplied, RESET must be held in the LOW state during
power up.
In the DDR DIMM application, RESET is specified to be completely
asynchronous with respect to CLK and CLK. Therefore, no timing
relationship can be guaranteed between the two. When entering
RESET, the register will be cleared and the outputs will be driven
LOW quickly, relative to the time to disable the differential input
receivers, thus ensuring no glitches on the output. However, when
coming out of RESET, the register will become active quickly, relative
to the time to enable the differential input receivers. When the data
inputs are LOW, and the clock is stable, during the time from the
LOW-to-HIGH transition of RESET until the input receivers
are fully enabled, the design must ensure that the outputs will
remain LOW.
Pericom’s PI74SSTVF16859 is characterized for operation from
0°C to 70°C.
TO 12 OTHER CHANNELS
Product Pin Description
Pin Name
Description
RESET
Reset (Active Low) LVCMOS
CLK
Clock Input, Positive Differential Input
CLK
Clock Input, Negative Differential Input
D
Data Input, D1-D13
Q
Data Output, Q1-Q13
GND
Ground
V_DD
V_DDQ
V_REF
Core Supply Voltage
Output Supply Voltage
Input Reference Voltage
Truth Table⁽¹⁾
Inputs
Outputs
RESET CLK
CLK
D
Q
L
X or
Floating
X or
Floating
X or
Floating
L
H
↑
↓
H
H
Η
↑
↓
L
L
H
L or H L or H
X
Qo⁽²⁾
Notes:
1. H = High Signal Level
2. Output level before the
L = Low Signal Level
indicated steady state
↑ = Transition LOW-to-HIGH
input conditions were
↓ = Transition HIGH-to-LOW
established.
X = Irrelevant or floating
1
PS8657
02/13/03