PI74SSTVF16857A Datasheet, PDF (1/8 Pages) Pericom Semiconductor Corporation – 14-Bit Registered Buffer

PI74SSTVF16857A
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14-Bit Registered Buffer
Product Features
Product Description
• Designed for low-voltage operation,
2.5V for PC1600 ~ PC2700; 2.6V for PC3200
• Supports SSTL_2 Class I output specifications
• SSTL_2 Input and Output Levels
• Designed for DDR Memory
• Flow-Through Architecture
• Packaging Options (Lead-free packages are available):
– 48-pin 240 mil wide plastic TSSOP (A)
– 48-pin 173 mil wide plastic TVSOP (K)
Pericom Semiconductor’s PI74SSTVF16857A series of logic circuits
are produced using the Company’s advanced sub-micron CMOS
technology, achieving industry leading speed.
The 14-bit PI74SSTVF16857A universal bus driver is designed
for 2.5V to 2.6V V_DD operation and SSTL_2 I/O Levels except for
the RESET input which is LVCMOS.
Data flow from D to Q is controlled by the differential clock , CLK,
CLK and RESET. Data is triggered on the positive edge of CLK.
CLK must be used to maintain noise margins.
Logic Block Diagram
38
CLK
39
CLK
RESET ³⁴
48
D1
35
V_REF
R
CLK
D
1 _Q1
RESET must be supported with LVCMOS levels as V_REF may not
be stable during power-up. RESET is asynchronous and is intended
for power-up only and when low assures that all of the registers reset
to the Low State, Q outputs are low, and all input receivers, data and
clock, are switched off.
Pericom’s PI74SSTVF16857A is characterized for operation from
0° to 70°C.
Product Pin Configuration
TO 13 OTHER CHANNELS
Product Pin Description
PinName Description
RESET
Reset (Active Low)
CLK
Clock Input
CLK
Clock Input
D
Data Input
Q
Data Output
GND
Ground
V_DD
Core Supply Voltage
V_DDQ
Output Supply Voltage
V_REF
Input Reference Voltage
Truth Table⁽¹⁾
Inputs
Outputs
RESET CLK CLK
D
Q
L
X
X
X
L
H
↑
↓
H
H
Η
↑
↓
L
H
L or H L or H
X
L
Qo⁽²⁾
Notes:
1. H = High Signal Level
2.
L = Low Signal Level
↑ = Transition LOW-to-HIGH
↓ = Transition HIGH-to-LOW
Output level before the
indicated steady state
input conditions were
established.
X = Irrelevant
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
Q7
VDDQ
GND
Q8
Q9
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10 ^48-Pin 39
11 ^A,K 38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLK
CLK
VDD
GND
VREF
RESET
D8
D9
D10
D11
D12
VDD
GND
D13
D14
1
PS8687
05/27/03