PI74LVTCH16245 Datasheet, PDF (1/7 Pages) Pericom Semiconductor Corporation – 3.3V 16-Bit Bi-Directional Transceiver with 3-State Outputs

PI74LVTCH16245
3.3V 16-Bit Bi-Directional Transceiver
with 3-State Outputs
Product Features
· Advanced low power CMOS design for 2.7V to 3.6V
Vcc operation
· Supports 5V input/output tolerance in mixed signal mode
operation
· Function compatible with LVT family of products
· Balanced ±24mA output drive
· Typical V_OLP (Output Ground Bounce) < 0.8V at V_CC=3.3V,
T_A=25°C
· I_off and Power Up/Down 3-State support live insertion
· Bus Hold on data inputs eliminates the need for external
pull-up/down resistors
· Latch-up performance exceeds 200mA Per JESD78
· ESD protection exceeds JESD 22
– 2000V Human-Body Model (A114-B)
– 200V Machine Model (A115-A)
· Industrial Temperature: –40°C to +85°C
· Packaging (Pb-free & Green available):
– 48-pin 240-mil wide plastic TSSOP (A)
Product Description
The PI74LVTCH16245 is a non-inverting 16-bit Bidirectional Trans-
ceiver designed for low-voltage 2.7V to 3.6V V_CC operation, with the
capability of interfacing to the 5V system environment. This
tranceiver is designed for asynchronous two-way communication
between data buses. The direction control input pin (xDIR) deter-
mines the direction of the data flow through the bidirectional
transceiver. The Direction and Output Enable controls are designed
to operate this device as either two independent 8-bit tranceivers
or one 16-bit transceiver. The output enable (xOE) input,
when HIGH, disables both A and B ports by placing them in
HIGH Z condition.
The PI74LVTCH16245 has "Bus Hold" which retains the data
input's last valid logic state whenever the data input goes to high-
impedance, preventing "floating" inputs and eliminating the need
for pull-up/down resistors.
When V_CC is between 0 to 1.5V during power up or power down, the
outputs of the device are in the high-impedance state. To ensure
the high-impedance state above 1.5V, OE should be tied to Vcc
through a pullup resistor; the minimum value of the resistor is
determined by the current sinking capability of the driver.
Logic Block Diagram
1
1DIR
1A0 ⁴⁷
1A1 ⁴⁶
1A2 ⁴⁴
1A3 ⁴³
1A4 ⁴¹
1A5 ⁴⁰
1A6 ³⁸
1A7 ³⁷
48 _1OE
2 _1B0
3 _1B1
5 _1B2
6 _1B3
8 _1B4
9 _1B5
11 _1B6
12 _1B7
24
2DIR
2A0 ³⁶
2A1 ³⁵
2A2 ³³
2A3 ³²
2A4 ³⁰
2A5 ²⁹
2A6 ²⁷
2A7 ²⁶
25 _2OE
13 _2B0
14 _2B1
16 _2B2
17 _2B3
19 _2B4
20 _2B5
22 _2B6
23 _2B7
The device fully supports live-insertion with its I_off and power-up/
down 3-state. The I_off circuitry disables the outputs when the
power is off, preventing the backflow of damaging current through
the device. Power-up/down 3-state places the outputs in the
high-impedance state during power up or power down, preventing
driver conflict.
06-0215
1
PS 8649C
03/14/07