PI74LVTC16244 Datasheet, PDF (1/8 Pages) Pericom Semiconductor Corporation – 3.3V 16-Bit Buffer/Line Driver with 3-State Outputs

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3.3V 16-Bit Buffer/Line Driver
with 3-State Outputs
Product Features
· Advanced low power CMOS design for 2.7V to 3.6V V_CC
operation
· Supports 5V input/output tolerance in mixed signal mode
operation
· Function compatible with LVT family of products
· Balanced ±24mA output drive
· Typical V_OLP (Output Ground Bounce)
<0.8V at V_CC=3.3V, T_A=25°C
· I_off and Power Up/Down 3-State support live insertion
· Latch-up performance exceeds 200mA Per JESD78
· ESD protection exceeds JESD 22
- 2000V Human-Body Model (A114-B)
- 200V Machine Model (A115-A)
· Available Packages (Pb-free available):
- 48-pin 240-mil wide plastic TSSOP (A48)
- 48-pin 300-mil wide plastic SSOP (V48)
· Industrial Temperature: -40°C to +85°C
Logic Block Diagram
Product Description
Pericom Semiconductor’s PI74LVTC series of logic circuits are
produced using the Company’s advanced CMOS technology,
achieving industry leading speed.
The PI74LVTC16244 is a non-inverting 16-bit buffer and line
driver designed for low-voltage 2.7V to 3.6V V_CC operation, with
the capability of interfacing to the 5V system environment. This
buffer/driver is designed specifically to improve both the perfor-
mance and density of 3-State memory address drivers, clock
drivers, and bus-oriented receivers and transmitters. The device
can be used as four 4-bit buffers, two 8-bit buffers, or one
16-bit buffer.
When V_CC is between 0 to 1.5V during power up or power down,
the device is in the high-impedance state. To ensure the high-
impedance state above 1.5V, OE should be tied to Vcc through a
pullup resistor; the minimum value of the resistor is determined by
the current sinking capability of the driver.
The device fully supports live-insertion with its I_off and power-up/
down 3-state. The I_off circuitry disables the outputs when the
power is off, preventing the backflow of damaging current through
the device. Power-up/down 3-state places the outputs in the high-
impedance state during power up or power down, preventing driver
conflict.
1OE ¹
1A1 ⁴⁷
2 _1Y1
3OE ²⁵
3A1 ³⁶
13 _3Y1
46
1A2
3
1Y2
35
3A2
14
3Y2
44
1A3
5
1Y3
33
3A3
16
3Y3
43
1A4
6
1Y4
32
3A4
17
3Y4
2OE ⁴⁸
2A1 ⁴¹
40
2A2
38
2A3
37
2A4
8 _2Y1
9 _2Y2
11 _2Y3
12 _2Y4
4OE ²⁴
4A1 ³⁰
29
4A2
27
4A3
26
4A4
19 _4Y1
20
4Y2
22
4Y3
23
4Y4
1
PS8652A
05/19/03