PI74FCT162511 Datasheet, PDF (1/8 Pages) Pericom Semiconductor Corporation – Fast CMOS 16-Bit Registered/Latched Transceiver With Parity

PI74FCT16511/162511T
16-BIT REGISTERED/
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PI74FCT162511T
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Product Features:
Common Features:
Fast CMOS 16-Bit Registered/Latched
Transceiver With Parity
• PI74FCT16511 and PI74FCT162511 are high-speed, low
power devices with high current drive.
• Vcc=5V±10%
• Typical tsk(o) (Output Skew) < 250 ps, clocked mode
• Extended range of –40°C to +85°C
• Hysteresis on all inputs
• Packages available:
– 56-pin 240 mil wide TSSOP (A)
– 56-pin 300 mil wide SSOP (V)
PI74FCT16511T Features:
• High output drive: IOH = –32 mA; IOL = 64 mA
• Power off disable outputs permit “live insertion”
• Typical VOLP (Output Ground Bounce) < 1.0V
at VCC = 5V, TA = 25°C
PI74FCT162511T Features:
• High output drive: IOL/IOH = 24 mA
• Open drain parity error allows wire-OR
• Typical VOLP (Output Ground Bounce) < 1.0V
at VCC = 5V, TA = 25°C
• Balanced output drivers: ±24 mA
• Series current limiting resistors
Simplified Logic Block Diagram
Product Description:
Pericom Semiconductor’s PI74FCT series of logic circuits are pro-
duced in the Company’s advanced 0.8 micron CMOS technology,
achieving industry leading speed grades.
The PI74FCT16511T and PI74FCT162511T are high-speed, low-
power 16-bit registered/latched transceiver with parity which
combines D-type latches and D-type flip-flops to allow data flow
in transparent, latched or clocked modes. It has a parity generator/
checker in the A-to-B direction and a parity checker in the B-to-A
direction. Error checking is done at the byte level with separate
parity bits for each byte. One error flag for each direction (A-to-B
or B-to-A) exists to indicate an error for either byte in either
direction. The parity error flags which are open drain outputs, can
be tied together and/or tied with flags from other devices to form a
single error flag or interrupt. To disable the error flag during
combinational transitions, a designer can disable the parity error
flag by the OExx control pins.
The operation in A-to-B direction is controlled by LEAB, CLKAB
and OEAB control pins, and the operation in B-to-A direction is
controlled by LEBA, CLKBA and OEBA control pins. GEN/CHK
is used to select the operation of A-to-B direction, while B-to-A
direction is always in checking mode. The ODD/EVEN select is
common between the two directions. Independent operation can be
achieved between the two directions by using the corresponding
control lines except for the ODD/EVEN control.
LEAB
CLKAB
GEN/CHK
A0-15
PA1,2
ODD/EVEN
OEBA
PERA
(Open Drain)
Data
16
Byte
Parity
Generator/
Checker
Parity
2
Latch/
Register
Parity, data
18
Parity, data
18
Latch/
Register
Parity, data
18
Byte
Parity
Checking
OEAB
B0-15
PB1,2
PERB
(Open Drain)
LEBA
CLKBA
1
PS2080A 01/15/95