PI74FCT16240T Datasheet, PDF (1/6 Pages) Pericom Semiconductor Corporation – Fast CMOS 16-Bit Buffer /Line Drivers

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PI74FCT162H240T
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Product Features:
Fast CMOS 16-Bit
Buffer/Line Drivers
Common Features:
• PI74FCT16240T,PI74FCT162240T,andPI74FCT162H240T
are high-speed,
low power devices with high current drive
• VCC = 5 V ±10%
Product Description:
Pericom Semiconductor’s PI74FCT series of logic circuits are pro-
duced in the Company’s advanced 0.6 micron CMOS technology,
achieving industry leading speed grades.
• Hysteresis on all inputs
• Packages available:
– 48-pin 240 mil wide plastic TSSOP (A)
– 48-pin 300 mil wide plastic SSOP (V)
PI74FCT16240T Features:
• High output drive: IOH = –32 mA; IOL = 64 mA
• Power off disable outputs permit "live insertion"
• Typical VOLP (Output Ground Bounce) < 1.0V
at VCC = 5V, TA = 25°C
PI74FCT162240T Features:
The PI74FCT16240T, PI74FCT162240T, and PI74FCT162H240T
are inverting 16-bit buffer/line drivers designed for applications
driving high capacitance loads and low impedance backplanes.
These high-speed, low power devices offer bus/backplane interface
capability and a flow-through organization for ease of board layout.
These devices are designed with three-state controls to operate in
a Quad-Nibble, Dual-Byte, or a single 16-bit word mode.
The PI74FCT16240T output buffers are designed with a Power-
Off disable allowing “live insertion” of boards when used as
backplane drivers.
• Balanced output drivers: ±24 mA
• Reduced system switching noise
• Typical VOLP (Output Ground Bounce) < 0.6V
at VCC = 5V, TA = 25°C
PI74FCT162H240T Features:
• Bus Hold retains last active bus state during 3-state
• Eliminates the need for external pull-up resistors
The PI74FCT162240T has ±24 mA balanced output drivers. It is
designed with current limiting resistors at its outputs to control the
output edge rate resulting in lower ground bounce and undershoot.
This eliminates the need for external terminating resistors for most
interface applications.
The PI74FCT162H240T has “Bus Hold” which retains the input's
last state whenever the input goes to high-impedance preventing
“floating” inputs and eliminating the need for pull-up/down resistors.
Logic Block Diagram
1OE
3OE
1A0
1Y0
3A0
3Y0
1A1
1Y1
3A1
3Y1
1A2
1Y2
3A2
3Y2
1A3
1Y3
3A3
3Y3
2OE
2A0
2A1
2A2
2A3
4OE
2Y0
4A0
2Y1
4A1
2Y2
4A2
2Y3
4A3
1
4Y0
4Y1
4Y2
4Y3
PS2030A 03/11/96