PI74AVC16268 Datasheet, PDF (1/11 Pages) Pericom Semiconductor Corporation – 12-Bit to 24-Bit Registered Bus Exchanger with 3-State Outputs

PI74AVC+16268 _{111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222}
12-Bit to 24-Bit Registered Bus
Exchanger with 3-State Outputs
Product Features
• PI74AVC+16268 is designed for low-voltage operation,
V_CC = 1.65V to 3.6V
• True ±24mA Balanced Drive @ 3.3V
• I_OFF supports partial power-down operation
• 3.6 I/O Tolerant Inputs and Outputs
• All outputs contain a patented DDC
(Dynamic DriveControl) circuit that reduces noise without
degrading propagation delay.
• Industrial operation: –40°C to +85°C
• Available Packages:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 173 mil wide plastic TVSOP (K)
Logic Block Diagram
CLK ²⁹
2
CLKEN1B
CLKEN2B ²⁷
CLKENA1 ³⁰
CLKENA2 ⁵⁵
OEB ⁵⁶
28
SEL
OEA ¹
A1 ⁸
C1
1D
1D
C1
G1
1
1
CE
C1
1D
1 of 12 Channels
Product Description
Pericom Semiconductor’s PI74AVC+ series of logic circuits are
produced using the Company’s advanced submicron CMOS
technology, achieving industry leading speed.
The PI74AVC+16268, a 12-bit to 24-bit registered bus exchanger
designed for 1.65V to 3.6V V_CC operation, is used for applications
in which data must be transferred from a narrow high-speed bus to
a wide, lower frequency bus. It provides synchronous data exchange
between the two ports. Data is stored in internal registers on the low-
to-high transition of the clock (CLK) input when appropriate clock-
enable (CLKEN) inputs are low. The select (SEL) line is synchronous
with CLK and selects 1B or 2B input data for the A outputs.
For data transfer in the A-to-B direction, a two-stage pipeline is
provided in the A-to-1B path, with a single storage register in the
A-to-2B path. Proper control of these inputs allows two sequential
12-bit words to be presented synchronously as a 24-bit word on the
B-port. Data flow is controlled by the active-low output enables
(OEA, OEB). These control terminals are registered so bus direction
changes are synchronous with CLK.
To ensure the high-impedance state during power up or power
down, a clock pulse should be applied as soon as possible and OE
should be tied to V_CC through a pullup resistor, the minimum value
of the resistor is determined by the current-sinking capability of the
driver. Because OE is being routed through a register, the active
state of the outputs cannot be determined prior to the arrival of the
first clock pulse.
C1
1D
CE
C1
1D
CE
C1
1D
CE
C1
1D
CE
C1
1D
23
1B1
6 _2B1
1
PS8551 07/31/01