PI74ALVCH16374 Datasheet, PDF (1/5 Pages) Pericom Semiconductor Corporation – 16-Bit Edge Triggered D-Type Flip-Flop with 3-State Outputs

PI74ALVCH16374
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16-Bit Edge Triggered D-Type Flip-Flop
with 3-State Outputs
Product Features
• PI74ALVCH16374 is designed for low voltage operation
• V_CC = 2.3V to 3.6V
• Hysteresis on all inputs
• Typical V_OLP (Output Ground Bounce)
< 0.8V at V_CC = 3.3V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
< 2.0V at V_CC = 3.3V, T_A = 25°C
• Bus Hold retains last active bus state during 3-STATE
eliminating the need for external pullup resistors
• Industrial operation at –40°C to +85°C
• Packages available:
– 48-pin 240 mil wide plastic TSSOP (A)
– 48-pin 300 mil wide plastic SSOP (V)
Logic Block Diagram
1OE ¹
1CLK ⁴⁸
47
1D1
C1
1D
2 _1Q1
Product Description
Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced in the Company’s advanced 0.5 micron CMOS technology,
achieving industry leading speed.
This 16-bit edge-triggered D-type flip-flop is designed for 2.3V to
3.6V V_CC operation.
The PI74ALVCH16374 is particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus drivers, and working
registers. This device can be used as two 8-bit flip-flops or one
16-bit flip-flop. On the positive transition of the Clock (CLK)
input, the Q outputs of the flip-flop take on the logic levels set up
at the data (D) inputs. OE can be used to place the eight outputs in
either a normal logic state (high or low logic levels) or a high-
impedance state. In that state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased
drive provide the capability to drive bus lines without need for
interface or pullup components. OE does not affect internal
operations of the flip-flop. Old data can be retained or new data can
be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to V_CC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
24
2OE
2CLK ²⁵
36
2D1
To Seven Other Channels
C1
1D
13 _2Q1
To Seven Other Channels
1
PS8138A 09/03/98