PI74ALVCH16373 Datasheet, PDF (1/5 Pages) Pericom Semiconductor Corporation – 16-Bit Transparent D-Type Latch with 3-STATE Outputs

PI74ALVCH16373 _{111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222}
16-Bit Transparent D-Type Latch
with 3-STATE Outputs
Product Features
• PI74ALVCH16373 is designed for low voltage operation
• V_CC = 2.3V to 3.6V
• Hysteresis on all inputs
• Typical V_OLP (Output Ground Bounce)
< 0.8V at V_CC = 3.3V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
< 2.0V at V_CC = 3.3V, T_A = 25°C
• Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
• Industrial operation at –40°C to +85°C
• Packages available:
– 48-pin 240 mil wide plastic TSSOP (A)
– 48-pin 300 mil wide plastic SSOP (V)
Logic Block Diagram
1OE ¹
1LE ⁴⁸
C1
47
1D1
1D
2 _1Q1
Product Description
Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced in the Company’s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
This 16-bit transparent D-type latch is designed for 2.3V to 3.6V
V_CC operation.
The PI74ALVCH16373 is particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus drivers, and working
registers. This device can be used as two 8-bit latches or one 16-bit
latch. When the Latch Enable (LE) input is HIGH, the Q outputs
follow the (D) inputs. When LE is taken LOW, the Q outputs are
latched at the levels set up at the D inputs.
A buffered Output Enable (OE) input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state in which the outputs neither
load nor drive the bus lines significantly. The high-impedance state
and the increased drive provide the capability to drive bus lines
without need for interface or pullup components. OE does not
affect internal operations of the latch. Old data can be retained
or new data can be entered while the outputs are in the high
impedance state.
To ensure the high impedance state during power up or power
down, OE should be tied to V_CC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
24
2OE
2LE ²⁵
36
2D1
To Seven Other Channels
C1
1D
13 _2Q1
To Seven Other Channels
1
PS8093B 10/09/00