PI74ALVCH162260 Datasheet, PDF (1/5 Pages) Pericom Semiconductor Corporation – 12-Bit To 24-Bit Multiplexed D-Type Latch with 3-STATE Outputs

PI74ALVCH162260
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PI74ALVCH162260
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12-Bit To 24-Bit Multiplexed D-Type Latch
with 3-STATE Outputs
Product Features
• PI74ALVCH162260 is designed for low voltage operation
• V_CC = 2.3V to 3.6V
• Hysteresis on all inputs
• Typical V_OLP (Output Ground Bounce)
< 0.8V at V_CC = 3.3V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
< 2.0V at V_CC = 3.3V, T_A = 25°C
• Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
• Industrial operation at –40°C to +85°C
• Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 300 mil wide plastic SSOP (V)
Logic Block Diagram
LE1B ²
LE2B ²⁷
30
LEA1B
LEA2B ⁵⁵
56
OE2B
29
OE1B
1
OEA
SEL ²⁸
A1 ⁸
G1
C1
1
1
1D
C1
1D
C1
1D
C1
1D
Product Description
Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced in the Company’s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The PI74ALVCH162260 is a 12-bit to 24-bit multiplexed D-type
latch designed for 2.3V to 3.6 VCC operation. It is used in
applications where two separate datapaths must be multiplexed
onto, or demultiplexed from, a single data path.
Typical applications include multiplexing and/or demulti-
plexing address and data information in microprocessor or
bus-interface applications. This device is also useful in
memory-interleaving applications.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are
available for address and/or data transfer. The output-enable
(OE1B, OE2B, and OEA) inputs control the bus transceiver
functions. The OE1B and OE2B control signals also allow bank
control in the A-to-B direction.
Address and/or data information can be stored using the
internal storage latches. The latch-enable (LE1B, LE2B, LEA1B,
and LEA2B) inputs are used to control data storage. When the
latch-enable input is HIGH, the latch is transparent. When the
latch-enable input goes LOW, the data present at the inputs
is latched and remains latched until the latch-enable input is
returned HIGH.
To reduce overshoot and undershoot, the B-port outputs
include 26Ω series resistors.
To ensure the high-impedance state during power up or power
down, OE should be tied to Vcc through a pullup resistor, the
minimum value of the resistor is determined by the current-
23
sinking capability of the driver.
1B1
Active bus-hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.
6
2B1
TO 11 OTHER CHANNELS
1
PS8127 03/17/98