PI6ULS5V9617A Datasheet, PDF (1/13 Pages) Pericom Semiconductor Corporation – Level Translating Fast-Mode Plus I2C-bus/SMbus Repeater

PI6ULS5V9617A
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Level Translating Fast-Mode Plus I²C-bus/SMbus Repeater
Features
 2 channel, bidirectional buffer isolates capacitance
and allows 540pF on either side of the device at 1
MHz and up to 4000 pF at lower speeds
 Voltage level translation from 0.6V to 5.5V and
from 2.2V to 5.5V
 Footprint and functional replacement for
PI6ULS5V9617A at Fast-mode speeds
 Port A operating supply voltage range of 0.6V to
5.5V with normal levels(0.4V_CC(A) + 0.8V ≤ V_CC(B) )
 Port B operating supply voltage range of 2.2V to
5.5V with static offset level
 5V tolerant I²C-bus and enable pins
 0 Hz to 1 MHz clock frequency (the maximum
system operating frequency may be less than 1MHz
because of the delays added by the repeater)
 Active HIGH repeater enable input referenced to
V_CC(B)
 Open-drain input/outputs
 Latching free operation
 Supports arbitration and clock stretching across the
repeater
 Accommodates Standard-mode, Fast-mode and
Fast-mode Plus I²C-bus devices, SMBus (standard
and high power mode), PMBus and multiple
masters
 Powered-off high-impedance I²C-bus pins
 ESD protection exceeds 8000V HBM per JESD22-
A114
 Package: MSOP-8L, SOIC-8L and TDFN2x3-8L
Description
The PI6ULS5V9617A is a CMOS integrated circuit
intended for Fast-mode Plus (Fm+) I²C-bus or SMBus
applications. It can provide level shifting between low
voltage (down to 0.6V) and higher voltage (2.2V to 5.5V)
in mixed-mode applications.
The PI6ULS5V9617A enables the system designer
to isolate two halves of a bus for both voltage and
capacitance, accommodating more I²C devices or longer
trace length. It also permits extension of the I²C-bus by
providing bidirectional buffering for both the data (SDA)
and the clock (SCL) lines, thus enabling two buses of
540 pF at 1 MHz or up to 4000 pF at lower speeds. The
SDA and SCL pins are overvoltage tolerant and are
high-impedance when the PI6ULS5V9617A is
unpowered.
The 2.2V to 5.5V bus port B drivers have the static
level offset, while the adjustable voltage bus port A
drivers eliminate the static offset voltage. This results in
a LOW on the port B translating into a nearly 0V LOW
on the port A which accommodates the smaller voltage
swings of lower voltage logic. The EN pin is referenced
to V_CC(B) and can also be used to turn the drivers on and
off under system control.
Pin Configuration
Pin Description
MSOP-8L, SOIC-8L(Top View)
Pin Name
V_CC(A)
SCLA
SDAA
GND
EN
SDAB
SCLB
V_CC(B)
Description
port A supply voltage (0.6V to 5.5V)
serial clock port A bus
serial data port A bus
supply ground (0 V)
active HIGH repeater enable input
serial data port B bus
serial clock port B bus
port B supply voltage (2.2V to 5.5V)
TDFN2*3-8L(Top View)
2014-03-0003
PT0482-3 04/09/14
1