PI6LC48S04 Datasheet, PDF (1/11 Pages) Pericom Semiconductor Corporation – HiFlex Serial Interface Clock

PI6LC48S04
HiFlex Serial Interface Clock
Features
ÎÎSelectable 250MHz, 156.25MHz, 125MHz or 100MHz output
clock synthesized from a 25MHz fundamental mode crystal
ÎÎFour differential clock outputs (two LVDS and two low power
HCSL outputs)
ÎÎCrystal interface designed for 25MHz, parallel resonant
crystal
ÎÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1MHz - 20MHz): 0.21ps (typical)
ÎÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal
(12kHz - 20MHz): 0.32ps (typical)
ÎÎPower supply noise rejection PSNR: -50dB (typical)
ÎÎLVCMOS interface levels for the frequency select input
ÎÎFull 3.3V or 2.5V supply voltage
ÎÎLead-free (RoHS 6) packaging
ÎÎ-40°C to 85°C ambient operating temperature
Description
The PI6LC48S04 is a 4-output clock synthesizer designed for se-
rial reference clock applications. The device generates four cop-
ies of a selectable 250MHz, 156.25MHz, 125MHz or 100MHz
clock signal with 0.34ps phase jitter performance. The four
outputs are organized in two banks of two LVDS and two low
power HCSL ouputs.The device supports 3.3V and 2.5V voltage
supplies and is packaged in a small 32-lead TQFN package.
Function Table
Inputs
F_SEL [1]
F_SEL [0]
0 (default)
0
1
0 (default)
1
0
1
1
Note: F_SEL[1:0] are asynchronous controls.
Output Frequency
with f_XTAL = 25MHz
156.25MHz
125MHz
100MHz
250MHz
Block Diagram
Pin Configuration
XTAL_IN
XTAL_OUT
REF_CLK
REF_SEL
BYPASS
F_SEL[0:1]
nOEA
nOEB
VSWING_CTRL
OSC
0
Pulldown
1
Pulldown
Pulldown
Pulldown 2
Pulldown
Pulldown
PFD
VCO
&
LPF
: 25
1
:N
0
QA0+
QA0-
LVDS
QA1+
QA1- ^LVDS
QB0+
QB0-
HCSL
QB1+
QB1-
HSCL
VDD
nc
VDDA
nc
GND
REF_CLK
nOEA
VDD
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
VSWING_CTRL
GND
QA0-
QA0+
VDDOA
QA1-
QA1+
GND
15-0128
1
PI6LC48S04 RevA
10/12/15