PI6LC4820 Datasheet, PDF (1/13 Pages) Pericom Semiconductor Corporation – HiFlex Ethernet Network Clock Generator

PI6LC4820
HiFlex^TM Ethernet Network Clock Generator
Features
ÎÎ3.3V supply voltage
ÎÎCrystal input: 25 MHz
ÎÎDifferential input: 25MHz, 156.25 MHz
ÎÎOutput frequencies of 312.5, 156.25, 125MHz supported
ÎÎ9 LVPECL or LVDS bank selectable outputs
ÎÎLow 1ps max integrated phase noise design
(12kHz to 20MHz)
ÎÎOptional xtal or clock input selection
ÎÎPLL Bypass mode for test
ÎÎPower supply noise rejection: -50 dBc typical @ 156.25 MHz
ÎÎPackaging (Pb-free & Green): 48-lead 7×7mm TQFN
Description
The PI6LC4820 is an LC VCO based low phase noise design
intended for 10GbE applications. Typical 10GbE usage assumes
a 25Mhz crystal input, while the PLL loop is used to generate
the 156.25MHz outputs. An additional buffered crystal oscilla-
tor output is provided to serve as a low noise reference for other
circuitry.
For Ethernet applications other than 10GbE, programmable
dividers allow for simultaneous output of 312.5, 156.25, and
125MHz.
Pin Configuration
FS0
X1
X2
V_{DD_OSC}
IN_SEL
PLL_BYPS
GND
FS1
QC_Mode
V_DDA
GND
V_{DD_PLL}
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
GND
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
V_{DD_QA}
QA0+
QA0-
QA1+
QA1-
QA2+
QA2-
QA3+
QA3-
QA4+
QA4-
V_{DD_QA}
13-0167
1
PI6LC4820 Rev D
11/13/13