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PI6CU877 Datasheet, PDF (1/11 Pages) Pericom Semiconductor Corporation – PLL Clock Driver for 1.8V DDR2 Memory
PI6CU877
PLL Clock Driver for
1.8V DDR2 Memory
Features
• PLL clock distribution optimized for DDR2 SDRAM
applications.
• Distributes one differential clock input pair to ten differential
clock output pairs.
• Differential Inputs (CLK, CLK) and (FBIN, FBIN)
• Input OE/OS: LVCMOS
• Differential Outputs (Y[0:9], Y[0:9] and (FBOUT, FBOUT)
• External feedback pins (FBIN, FBIN) are used to
synchronize the outputs to the clock input.
• Operates at AVDD = 1.8V for core circuit and internal PLL,
and VDDQ = 1.8V for differential output drivers
• Packaging (Pb-free & Green available):
– 52-ball VFBGA (NF)
Pin Configuration
1
2
3
4
5
6
A Y1
Y0
Y0
Y5
Y5
Y6
Description
PI6CU877 PLL clock driver is developed for Registered DDR2
DIMM applications with 1.8V operation and differential data input
and output levels.
The device is a zero delay buffer that distributes a differential
clock input pair (CLK, CLK) to eleven differential pairs of clock
outputs which includes feedback clock (Y[0:9], Y[0:9]; FBOUT,
FBOUT).
The clock outputs are controlled by CLK/CLK, FBOUT, FBOUT, the
LVCMOS (OE, OS) and the Analog Power input (AVDD). When
OE is LOW the outputs except FBOUT, FBOUT, are disabled while
the internal PLL continues to maintain its locked-in frequency.
OS is a program pin that must be tied to GND or VDD. When OS
is high, OE will function as described above. When OS is LOW,
OE has no effect on Y7/Y7, they are free running. When AVDD is
grounded, the PLL is turned off and bypassed for test purposes.
When CLK/CLK are logic low, the device will enter a low power
mode. An input logic detection circuit will detect the logic low level
and perform a low power state where all Y[0:9], Y[0:9]; FBOUT,
FBOUT, and PLL are OFF.
PI6CU877 is a high performance, low skew, and low jitter PLL
clock driver, and it is also able to track Spread Spectrum Clocking
(SSC) for reduced EMI.
B Y1
GND GND GND GND
Y6
C Y2
GND
NB
NB
GND
Y7
D
Y2
VDDQ VDDQ VDDQ
OS
Y7
E
CK
VDDQ
NB
NB
VDDQ FBIN
F
CK
VDDQ
NB
NB
OE
FBIN
G AGND VDDQ VDDQ VDDQ VDDQ FBOUT
H AVDD GND
NB
NB
GND FBOUT
J
Y3
GND GND GND GND
Y8
k
Y3
Y4
Y4
Y9
Y9
Y8
1
PS8689B
08/05/04
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