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| PI6CEQ20200 Datasheet, PDF (1/9 Pages) Pericom Semiconductor Corporation – PCIe Gen2 / Gen3 Buffer | |||
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Features
ÃÃPCIe Gen2/ Gen3* compliant clock buffer/ZDB
* Gen3 performance only available in Commercial temp
ÃÃInternal equalization for better signal integrity
ÃÃ2 HCSL outputs
ÃÃDual PLL bandwidth for SSC tracking
ÃÃCycle-to-Cycle Jitter : 40ps (typ)
ÃÃOutput-to-Output Skew <10ps
ÃÃ3.3V supply voltage
ÃÃTSSOP-20 packages
Applications
ÃÃServers
ÃÃEmbedded computing systems
ÃÃNetworking systems
Block Diagram
PI6CEQ20200
PCIe® Gen2 / Gen3 Buffer
Description
The PI6CEQ20200 is a high performance PCIe Gen2/ Gen3
zero delay buffer with two HCSL outputs. Pericomâs proprietary
equalization technique used in this device improves signal
integrity and makes this device suitable for PCIe Gen2/ Gen3
applications even when the input from the main clock has to
travel a long distance.
Pin Configuration (20-Pin TSSOP & 20-Pin QSOP)
SRCIN
SRCIN#
EQ
PLL
PLL_BW_SEL
SCLK
SDATA
Control
OE0#
CLK0
CLK0#
OE1#
CLK1
CLK1#
PLL_BW_SEL 1
SRCIN 2
SRCIN# 3
OE_0# 4
VDD 5
GND 6
CLK0 7
CLK0# 8
VDD 9
SDATA 10
20 VDDA
19 GNDA
18 IRef
17 OE_1#
16 VDD
15 GND
14 CLK1
13 CLK1#
12 VDD
11 SCLK
15-0058
1
www.pericom.com
Rev B
05/05/15
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