PI6CDBL402B Datasheet, PDF (1/13 Pages) Pericom Semiconductor Corporation – 4 -Output Low Power PCIE GEN 1-2-3 Buffer

PI6CDBL402B
4 -Output Low Power PCIE GEN 1-2-3 Buffer
Features
ÎÎPhase jitter filter for PCIe 3.0/ 2.0/ 1.0 application
ÎÎLow power consumption with independent output power
supply 1.8V~3.3V
ÎÎLow skew < 60ps
ÎÎLow cycle-to-cycle jitter - 45ps (typ.) @100MHz
ÎÎ< 1 ps additive RMS phase jitter
ÎÎOutput Enable for all outputs
ÎÎProgrammable PLL Bandwidth
ÎÎ100 MHz PLL Mode operation
ÎÎ1 - 400 MHz Bypass Mode operation
ÎÎ3.3V Operation
ÎÎPackaging (Pb-free and Green):
-28-Pin TSSOP (L28)
Block Diagram
Description
Pericom Semiconductor's PI6CDBL402B is a PCIe 3.0 compliant
high-speed, low-noise differential clock buffer designed to be
companion to PCIe 3.0 clock generator. It is backward compat-
ible with PCIe 1.0 and 2.0 specification.
The device distributes the differential SRC clock from PCIe 3.0
clock generator to four differential pairs of clock outputs either
with or without PLL. The clock outputs are controlled by input
selection of PWRDWN# and SMBus, SCLK and SDA.
Pin Configuration
OE_INV
OE_0 & OE_3
PWRDWN#
Output
Control
SCLK
SDA
PLL/BYPASS#
SRC
SRC#
SMBus
Controller
PLL_BW#
PLL
OUT0
OUT0#
OUT1
OUT1#
OUT2
OUT2#
OUT3
OUT3#
VDD 1
SRC 2
SRC# 3
GND 4
VDDO 5
OUT0 6
OUT0# 7
OE_0 8
OUT1 9
OUT1# 10
VDDO 11
PPLLLL/B/BYYPPAASSSS# 12
SCLK 13
SDA 14
28 VDD_A
27 GNDA
26 NC
25 OE_INV
24 VDDO
23 OUT3
22 OUT3#
21 OE_3
20 OUT2
19 OUT2#
18 VDDO
17 PLL_BW#
16 VDD
15 PWRDWN#
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www.pericom.com 06/30/15