PI6C49S1510 Datasheet, PDF (1/16 Pages) Pericom Semiconductor Corporation – High Performance Differential Fanout Buffer

PI6C49S1510
High Performance Differential Fanout Buffer
Features
ÎÎ10 differential outputs with 2 banks
ÎÎUser configurable output signaling standard for each bank:
LVDS or LVPECL or HCSL
ÎÎLVCMOS reference output up to 200MHz
ÎÎUp to 1.5GHz output frequency for differential outputs
ÎÎUltra low additive phase jitter: < 0.03 ps (typ) (differential
156.25MHz, 12KHz to 20MHz integration range); < 0.02 ps
(typ) (differential 156.25MHz, 10kHz to 1MHz integration
range)
ÎÎSelectable reference inputs support either single-ended
or differential or Xtal
ÎÎLow skew between outputs within banks (<40ps)
ÎÎLow delay from input to output (Tpd typ. < 1.7ns)
ÎÎSeparate Input output supply voltage for level shifting
ÎÎ2.5V / 3.3V power supply
ÎÎIndustrial temperature support
ÎÎTQFN-48 package
Description
The PI6C49S1510 is a high performance fanout buffer device-
which supports up to 1.5GHz frequency. It also integrates a
unique feature with user configurable output signaling stan-
dards on per bank basis which provide great flexibilities to
users. The device also uses Pericom's proprietary input detection
technique to make sure illegal input conditions will be detected
and reflected by output states. This device is ideal for systems
that need to distribute low jitter clock signals to multiple desti-
nations.
Applications
ÎÎNetworking systems including switches and Routers
ÎÎHigh frequency backplane based computing and telecom
platforms
Block Diagram
Pin Configuration (48-Pin TQFN)
X1
X2
IN0+
IN0-
IN1+
IN1-
OSC
IN_SEL[1:0]
Sync_OE
Iref
Sync
OPMODEA[1:0]
QA[0:4]
5
OPMODEB[1:0]
QB[0:4]
5
Ref_Out
QAO+
QAO-
QA1+
QA1-
VDDO
QA2+
QA2-
VDDO
QA3+
QA3-
QA4+
QA4-
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
QBO+
QBO-
QB1+
QB1-
VDDO
QB2+
QB2-
VDDO
QB3+
QB3-
QB4+
QB4-
14-0137
1
PI6C49S1510
Rev G
09/18/2014