PI6C4911504D2 Datasheet, PDF (1/14 Pages) Pericom Semiconductor Corporation – LVPECL Clock Buffer

PI6C4911504D2
LVPECL Clock Buffer with ÷2 Feature
Features
ÎÎ2 pairs of selectable differential inputs
ÎÎ2 divide by 2 differential LVPECL outputs and 2 buffered
outputs
ÎÎMaximum operating frequency: 650MHz
ÎÎRMS additive jitter @ 156.25MHz (12kHz – 20MHz): 30fs
(typical)
ÎÎOutput skew: 60ps
ÎÎPart to part skew: 200ps
ÎÎOperating voltage of 2.5V and 3.3V
ÎÎIndustrial operating temperature
ÎÎAvailable in lead-free package
Description
PI6C4911504D2 is a high performance differential buffer with
divide by 2 capability. There are also 2 selectable muxed inputs.
This device is ideal for systems that need to distribute low jitter
clock signals to multiple destinations with a change from the
input frequency.
Applications
ÎÎNetworking: 10GbE, 25GbE, 40GbE and 100GbE
applications
ÎÎTelecom: Basestations and Access Points
Block Diagram
CLK_EN
D
Q
LE
REF_IN0+
REF_IN0-
0
÷1
REF_IN1+
REF_IN1-
1
÷2
CLK_SEL
M_RESET
CLKA[0:1]
CLKA[0:1]#
2
CLKB[0:1]
CLKB[0:1]#
2
15-0101
1 ^{www.pericom.com}
PI6C4911504D2 Rev D
07/23/15