PI6C49003A Datasheet, PDF (1/12 Pages) Pericom Semiconductor Corporation – PCIe Gen 2 Networking Clock Generator

PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Features
• 3.3V +/-10% Supply Voltage
• Uses 25MHz xtal
• Five PCIe® Gen. 2 100MHz HCSL outputs with optional
-0.5% spread spectrum support
• Two LVCMOS 50MHz outputs that support +/- 10%
frequency margining
• One frequency selectable 33/66/133MHz LVCMOS output
• One 32.256MHz LVCMOS output
• Industrial temperature -40°C to 85°C
• Package: 48-pin TSSOP package
Description
The PI6C49003A is a clock generator device intended for PCIe®
Gen2 networking applications. The device includes five 100MHz
differential Host Clock Signal Level (HCSL) outputs for PCIe Gen
2, two single-ended 50MHz outputs, one single-ended 32.256MHz
output, and one selectable single-ended 33/66/133MHz output.
Using a serially programmable SMBUS interface, the PI6C49003A
incorporates spread spectrum modulation on the twelve 100MHz
HCSL PCIe Gen 2 outputs, and independent frequency margining
on the 50MHz output, 33.3333MHz and 66.6666MHz clock
outputs.
Block Diagram
VDD
14
25 MHz
crystal or
clock input
Clock Buffer/
Crystal
Oscillator
5
SCLK
SDATA
PD_RESET
PLL, Dividers,
Buffers, and
Logic
10
GND
ISET
475 Ohms
1%
Pin Configuration
100M_OUT(0-4)
50M_OUT(1-2)
33/66/133M_OUT1
32.256M_OUT1
VDD
1
IREF
2
NC
3
NC
4
VDD
5
VDD
6
GND
7
GND
8
VDD
9
GND
10
VDD
11
SCLK
12
SDATA
13
GND
14
50M_Out1
15
50M_Out2
16
VDD
17
GND
18
VDD
19
32.256M_Out1
20
GND
21
NC
22
NC
23
PD_RESET
24
48
GND
47
VDD
46
100M_Q0-
45
100M_Q0+
44
100M_Q1+
43
100M_Q1-
42
VDD
41
GND
40
VDD
39
100M_Q2+
38
100M_Q2-
37
100M_Q3+
36
100M_Q3-
35
VDD
34
GND
33
VDD
32
100M_Q4+
31
100M_Q4-
30
33/66/133M_Out1
29
VDD
28
GND
27
VDD
26
X2
25
X1
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14-0198
1
www.pericom.com 11/11/14