PI6C48545 Datasheet, PDF (1/5 Pages) Pericom Semiconductor Corporation – 3.3V Low Skew 1-to-4 LVTTL/LVCMOS to LVDS Fanout Buffer

PI6C48545
3.3V Low Skew 1-to-4
LVTTL/LVCMOS to LVDS Fanout Buffer
Features
• Maximum operation frequency: 650 MHz
• 4 pair of differential LVDS outputs
• Selectable CLK₀ and CLK₁ inputs
• CLK₀, CLK₁ accept LVCMOS, LVTTL input level
• Output Skew: 40ps (maximum)
• Part-to-part skew: 300ps (maximum)
• Propagation delay: 2.2ns (maximum)
• 3.3V power supply
• Pin-to-pin compatible to ICS8545
• Operating Temperature: -40^oC to 85^oC
• Packaging (Pb-free & Green):
- 20-pin TSSOP (L)
Description
The PI6C48545 is a high-performance low-skew LVDS fanout
buffer. PI6C48545 features two selectable single-ended clock in-
puts and translate to four LVDS outputs. The CLK₀ and CLK₁
inputs accept LVCMOS or LVTTL signals. The outputs are
synchronized with input clock during asynchronous assertion/
deassertion of CLK_EN pin. PI6C48545 is ideal for single-ended
LVTTL/LVCMOS to LVDS translations. Typical clock transla-
tion and distribution applications are data-communications and
telecommunications.
Block Diagram
CLK_EN
CLK0
CLK1
D
Q
LE
0
1
CLK_SEL
OE
Pin Diagram
GND 1
CLK_EN 2
CLK_SEL 3
Q0
CLK0 4
nQ0
NC 5
Q₁
nQ1
CLK1 6
NC 7
OE 8
Q2
GND 9
nQ2
VCC 10
Q3
n^Q3
20 Q0
19 nQ0
18 VCC
17 Q1
16 nQ1
15 Q2
14 nQ2
13 GND
12 Q3
11 nQ3
1
PS8770
06/23/05