PI6C48543 Datasheet, PDF (1/7 Pages) Pericom Semiconductor Corporation – 3.3V Low Skew 1-to-4, 800MHz, Differential to LVDS Fanout Buffer

PI6C48543
3.3V Low Skew 1-to-4, 800MHz,
Differential to LVDS Fanout Buffer
Features
• Maximum operation frequency: 800 MHz
• 4 pair of differential LVDS outputs
• Selectable differential CLK and PCLK inputs
• CLK, _nCLK pair accepts LVDS, LVPECL, LVHSTL, SSTL
and HCSL input level
• PCLK, nPCLK pair supports LVPECL, CML and SSTL
input level
• Output Skew: 40ps (maximum)
• Part-to-part skew: 300ps (maximum)
• Propagation delay: 2.2ns (maximum)
• 3.3V power supply
• Pin-to-pin compatible to ICS8543
• Operating Temperature: -40^oC to 85^oC
• Packaging (Pb-free & Green):
-20-pin TSSOP (L)
Description
The PI6C48543 is a high-performance low-skew LVDS fanout
buffer. PI6C48543 features two selectable differential inputs and
translates to four LVDS outputs. The inputs can also be configured
to single-ended with external resistor bias circuit. The CLK input
accepts LPECL or LVDS or LVHSTL or SSTL or HCSL signals,
and PCLK input accepts LVPECL or SSTL or CML signals. The
outputs are synchronized with input clock during asynchronous
assertion/deassertion of CLK_EN pin. PI6C48543 is ideal for
differential to LVDS translations and/or LVDS clock distribution.
Typical clock translation and distribution applications are data-
communications and telecommunications.
Block Diagram
CLK_EN
CLK
nCLK
PCLK
nPCLK
D
Q
LE
0
1
CLK_SEL
OE
Pin Diagram
GND 1
CLK_EN 2
CLK_SEL 3
CLK 4
nCLK 5
Q0
PCLK 6
nQ0
nPCLK 7
Q1
OE 8
nQ1
GND 9
VCC 10
Q2
nQ2
Q3
nQ3
20 Q₀
19 _nQ₀
18 V_CC
17 Q₁
16 _nQ₁
15 Q₂
14 _nQ₂
13 GND
12 Q₃
11 _nQ₃
08-0247
1
PS8771B
10/02/08